3230 	u8 lane = 0;  in bnx2x_get_warpcore_lane()  local
3261 		lane = (port<<1) + path;  in bnx2x_get_warpcore_lane()
3276 		lane = path << 1 ;  in bnx2x_get_warpcore_lane()
3278 	return lane;  in bnx2x_get_warpcore_lane()
3553 		u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_ext_phy_update_adv_fc()  local
3560 			lane;  in bnx2x_ext_phy_update_adv_fc()
3725 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_restart_AN_KR()  local
3727 			  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_warpcore_restart_AN_KR()
3738 	u16 lane, i, cl72_ctrl, an_adv = 0, val;  in bnx2x_warpcore_enable_AN_KR()  local
3791 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_enable_AN_KR()
3793 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_enable_AN_KR()
3798 				 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),  in bnx2x_warpcore_enable_AN_KR()
3843 				  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_warpcore_enable_AN_KR()
3846 					 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),  in bnx2x_warpcore_enable_AN_KR()
3862 				MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);  in bnx2x_warpcore_enable_AN_KR()
3872 		    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))  in bnx2x_warpcore_enable_AN_KR()
3877 				 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),  in bnx2x_warpcore_enable_AN_KR()
3892 	u16 val16, i, lane;  in bnx2x_warpcore_set_10G_KR()  local
3910 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_KR()
3917 	val16 &= ~(0x0011 << lane);  in bnx2x_warpcore_set_10G_KR()
3923 	val16 |= (0x0303 << (lane << 1));  in bnx2x_warpcore_set_10G_KR()
3960 	u16 misc1_val, tap_val, tx_driver_val, lane, val;  in bnx2x_warpcore_set_10G_XFI()  local
4060 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_XFI()
4065 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_set_10G_XFI()
4146 					 u16 lane)  in bnx2x_warpcore_set_20G_DXGXS()  argument
4194 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_set_20G_DXGXS()
4300 				      u16 lane)  in bnx2x_warpcore_clear_regs()  argument
4328 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_clear_regs()
4330 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);  in bnx2x_warpcore_clear_regs()
4394 	u16 gp2_status_reg0, lane;  in bnx2x_warpcore_get_sigdet()  local
4397 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_get_sigdet()
4402 	return (gp2_status_reg0 >> (8+lane)) & 0x1;  in bnx2x_warpcore_get_sigdet()
4419 		u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_runtime()  local
4430 			lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */  in bnx2x_warpcore_config_runtime()
4432 			lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;  in bnx2x_warpcore_config_runtime()
4461 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_sfi()  local
4463 	bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_sfi()
4503 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_init()  local
4520 		bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4535 			bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4578 			bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);  in bnx2x_warpcore_config_init()
4608 	u16 val16, lane;  in bnx2x_warpcore_link_reset()  local
4633 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_link_reset()
4637 	val16 |= (0x11 << lane);  in bnx2x_warpcore_link_reset()
4639 		val16 |= (0x22 << lane);  in bnx2x_warpcore_link_reset()
4645 	val16 &= ~(0x0303 << (lane << 1));  in bnx2x_warpcore_link_reset()
4646 	val16 |= (0x0101 << (lane << 1));  in bnx2x_warpcore_link_reset()
4648 		val16 &= ~(0x0c0c << (lane << 1));  in bnx2x_warpcore_link_reset()
4649 		val16 |= (0x0404 << (lane << 1));  in bnx2x_warpcore_link_reset()
4664 	u32 lane;  in bnx2x_set_warpcore_loopback()  local
4680 		lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_set_warpcore_loopback()
4683 		val16 |= (1<<lane);  in bnx2x_set_warpcore_loopback()
4685 			val16 |= (2<<lane);  in bnx2x_set_warpcore_loopback()
5703 	u8 lane;  in bnx2x_warpcore_read_status()  local
5706 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_read_status()
5736 			(1 << lane);  in bnx2x_warpcore_read_status()
5752 				if (gp_status4 & ((1<<12)<<lane))  in bnx2x_warpcore_read_status()
5797 	if (lane < 2) {  in bnx2x_warpcore_read_status()
5804 	DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);  in bnx2x_warpcore_read_status()
5806 	if ((lane & 1) == 0)  in bnx2x_warpcore_read_status()
6480 			u8 lane = bnx2x_get_warpcore_lane(int_phy, params);  in bnx2x_test_link()  local
6486 			link_up = gp_status & (1 << lane);  in bnx2x_test_link()
8646 	u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_limiting_mode()  local
8650 	val &= ~(0xf << (lane << 2));  in bnx2x_warpcore_set_limiting_mode()
8665 	val |= (mode << (lane << 2));  in bnx2x_warpcore_set_limiting_mode()
13725 	u16 base_page, next_page, not_kr2_device, lane;  in bnx2x_check_kr2_wa()  local
13747 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_check_kr2_wa()
13749 			  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_check_kr2_wa()