1487 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_init()
1490 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_emac_init()
1562 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_umac_enable()
1566 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_umac_enable()
1677 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1681 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1707 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1711 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1825 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_enable()
2417 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_bmac_enable()
2422 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_bmac_enable()
3341 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_serdes_deassert()
3343 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_serdes_deassert()
3377 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_xgxs_deassert()
3379 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_xgxs_deassert()
6622 	REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,  in bnx2x_int_link_reset()
12731 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
12735 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
12994 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_link_reset()