Lines Matching refs:bnx2_write_phy
547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) in bnx2_write_phy() function
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); in bnx2_5709s_linkup()
1117 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_5709s_linkup()
1389 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_bmsr1()
1398 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_bmsr1()
1415 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_enable_2g5()
1420 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1425 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_enable_2g5()
1441 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_disable_2g5()
1446 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1451 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_disable_2g5()
1469 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1475 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_enable_forced_2g5()
1478 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1498 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1513 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1517 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_disable_forced_2g5()
1520 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1537 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1545 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); in bnx2_5706s_force_link_dn()
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1550 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1584 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_set_link()
1621 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1643 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1811 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1814 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1819 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1822 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1823 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1845 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1851 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1852 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
2104 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2105 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); in bnx2_setup_copper_phy()
2106 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2121 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2138 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2147 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); in bnx2_init_5709s_phy()
2195 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); in bnx2_init_5709s_phy()
2197 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2201 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); in bnx2_init_5709s_phy()
2206 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); in bnx2_init_5709s_phy()
2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_init_5709s_phy()
2214 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); in bnx2_init_5709s_phy()
2216 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); in bnx2_init_5709s_phy()
2219 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); in bnx2_init_5709s_phy()
2221 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); in bnx2_init_5709s_phy()
2225 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); in bnx2_init_5709s_phy()
2227 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); in bnx2_init_5708s_phy()
2243 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); in bnx2_init_5708s_phy()
2244 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2248 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); in bnx2_init_5708s_phy()
2252 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); in bnx2_init_5708s_phy()
2257 bnx2_write_phy(bp, BCM5708S_UP1, val); in bnx2_init_5708s_phy()
2264 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2268 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); in bnx2_init_5708s_phy()
2269 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2280 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2282 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); in bnx2_init_5708s_phy()
2283 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2305 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2307 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2309 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2311 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2316 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2318 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2320 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2322 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2337 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2338 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2339 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2340 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2341 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2342 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2343 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2344 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2348 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, in bnx2_init_copper_phy()
2352 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); in bnx2_init_copper_phy()
2357 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2359 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2362 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2365 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2367 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2370 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2374 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); in bnx2_init_copper_phy()
2382 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); in bnx2_init_copper_phy()
2455 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
6052 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); in bnx2_5706_serdes_has_link()
6058 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_has_link()
6065 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); in bnx2_5706_serdes_has_link()
6095 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6104 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6111 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6121 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_timer()
7164 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7178 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7869 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()