278 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
316 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
496 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
500 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
513 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
517 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
534 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
538 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
553 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
557 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
570 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
583 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
587 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
606 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
1329 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1371 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1582 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
2438 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2467 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2578 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2603 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
3368 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3379 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3435 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3483 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3983 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
4018 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4057 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4062 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4112 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4135 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4154 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4167 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4183 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4193 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4204 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4240 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4282 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4284 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4331 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4353 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4778 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_reset_chip()
4781 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4784 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_reset_chip()
4788 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_reset_chip()
4804 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4808 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4834 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4849 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4918 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4953 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4972 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
5099 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5107 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5111 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5247 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5847 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5873 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
6022 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6026 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6029 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6271 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6516 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6525 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6529 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6530 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6531 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6552 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6553 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6555 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6557 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6560 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
7087 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7703 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7933 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7973 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7979 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
8167 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8232 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8396 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()