55 static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val)  in nb8800_writeb()  function
77 		nb8800_writeb(priv, reg, new);  in nb8800_maskb()
626 	nb8800_writeb(priv, NB8800_IC_THRESHOLD, ict);  in nb8800_mac_config()
627 	nb8800_writeb(priv, NB8800_SLOT_TIME, slot_time);  in nb8800_mac_config()
702 		nb8800_writeb(priv, NB8800_SRC_ADDR(i), dev->dev_addr[i]);  in nb8800_update_mac_addr()
705 		nb8800_writeb(priv, NB8800_UC_ADDR(i), dev->dev_addr[i]);  in nb8800_update_mac_addr()
725 	nb8800_writeb(priv, NB8800_MC_INIT, val);  in nb8800_mc_init()
746 			nb8800_writeb(priv, NB8800_MC_ADDR(i), ha->addr[i]);  in nb8800_set_rx_mode()
1165 	nb8800_writeb(priv, NB8800_STAT_INDEX, index);  in nb8800_read_stat()
1202 	nb8800_writeb(priv, NB8800_TX_CTL1, val);  in nb8800_hw_init()
1205 	nb8800_writeb(priv, NB8800_TX_CTL2, 5);  in nb8800_hw_init()
1208 	nb8800_writeb(priv, NB8800_RX_CTL, val);  in nb8800_hw_init()
1211 	nb8800_writeb(priv, NB8800_RANDOM_SEED, 4);  in nb8800_hw_init()
1214 	nb8800_writeb(priv, NB8800_TX_SDP, 12);  in nb8800_hw_init()
1221 	nb8800_writeb(priv, NB8800_PE_THRESHOLD, 0);  in nb8800_hw_init()
1224 	nb8800_writeb(priv, NB8800_PF_THRESHOLD, 255);  in nb8800_hw_init()
1227 	nb8800_writeb(priv, NB8800_TX_BUFSIZE, 64);  in nb8800_hw_init()
1273 	nb8800_writeb(priv, NB8800_PQ1, val >> 8);  in nb8800_hw_init()
1274 	nb8800_writeb(priv, NB8800_PQ2, val & 0xff);  in nb8800_hw_init()
1311 	nb8800_writeb(priv, NB8800_TANGOX_PAD_MODE, pad_mode);  in nb8800_tangox_init()
1321 	nb8800_writeb(priv, NB8800_TANGOX_RESET, 0);  in nb8800_tangox_reset()
1323 	nb8800_writeb(priv, NB8800_TANGOX_RESET, 1);  in nb8800_tangox_reset()