Lines Matching refs:p
26 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) in xgene_enet_wr_csr() argument
28 iowrite32(val, p->eth_csr_addr + offset); in xgene_enet_wr_csr()
31 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p, in xgene_enet_wr_ring_if() argument
34 iowrite32(val, p->eth_ring_if_addr + offset); in xgene_enet_wr_ring_if()
37 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p, in xgene_enet_wr_diag_csr() argument
40 iowrite32(val, p->eth_diag_csr_addr + offset); in xgene_enet_wr_diag_csr()
72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *p, in xgene_enet_wr_mac() argument
76 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, in xgene_enet_wr_mac()
77 .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, in xgene_enet_wr_mac()
78 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, in xgene_enet_wr_mac()
79 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET in xgene_enet_wr_mac()
83 netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr); in xgene_enet_wr_mac()
86 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() argument
88 return ioread32(p->eth_csr_addr + offset); in xgene_enet_rd_csr()
91 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_diag_csr() argument
93 return ioread32(p->eth_diag_csr_addr + offset); in xgene_enet_rd_diag_csr()
120 static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr) in xgene_enet_rd_mac() argument
123 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, in xgene_enet_rd_mac()
124 .ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET, in xgene_enet_rd_mac()
125 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, in xgene_enet_rd_mac()
126 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET in xgene_enet_rd_mac()
132 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) in xgene_enet_ecc_init() argument
134 struct net_device *ndev = p->ndev; in xgene_enet_ecc_init()
138 xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); in xgene_enet_ecc_init()
141 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); in xgene_enet_ecc_init()
150 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) in xgene_enet_config_ring_if_assoc() argument
154 val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0; in xgene_enet_config_ring_if_assoc()
155 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
156 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
159 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, in xgene_mii_phy_write() argument
166 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
169 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
172 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_write()
178 netdev_err(p->ndev, "MII_MGMT write failed\n"); in xgene_mii_phy_write()
181 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) in xgene_mii_phy_read() argument
187 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
188 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
191 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_read()
193 data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); in xgene_mii_phy_read()
194 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
201 netdev_err(p->ndev, "MII_MGMT read failed\n"); in xgene_mii_phy_read()
206 static void xgene_sgmac_reset(struct xgene_enet_pdata *p) in xgene_sgmac_reset() argument
208 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_sgmac_reset()
209 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); in xgene_sgmac_reset()
212 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) in xgene_sgmac_set_mac_addr() argument
215 u8 *dev_addr = p->ndev->dev_addr; in xgene_sgmac_set_mac_addr()
219 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); in xgene_sgmac_set_mac_addr()
221 addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); in xgene_sgmac_set_mac_addr()
223 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); in xgene_sgmac_set_mac_addr()
226 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p) in xgene_enet_link_status() argument
230 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_enet_link_status()
236 static void xgene_sgmac_init(struct xgene_enet_pdata *p) in xgene_sgmac_init() argument
239 u32 offset = p->port_id * 4; in xgene_sgmac_init()
243 xgene_sgmac_reset(p); in xgene_sgmac_init()
246 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000); in xgene_sgmac_init()
247 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); in xgene_sgmac_init()
250 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_sgmac_init()
257 netdev_err(p->ndev, "Auto-negotiation failed\n"); in xgene_sgmac_init()
259 data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); in xgene_sgmac_init()
261 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2); in xgene_sgmac_init()
262 xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE); in xgene_sgmac_init()
264 if (p->enet_id == XGENE_ENET1) { in xgene_sgmac_init()
276 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); in xgene_sgmac_init()
278 xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); in xgene_sgmac_init()
280 xgene_sgmac_set_mac_addr(p); in xgene_sgmac_init()
283 data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); in xgene_sgmac_init()
285 xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); in xgene_sgmac_init()
288 data = xgene_enet_rd_csr(p, rsif_config_reg); in xgene_sgmac_init()
290 xgene_enet_wr_csr(p, rsif_config_reg, data); in xgene_sgmac_init()
293 xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); in xgene_sgmac_init()
294 xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); in xgene_sgmac_init()
295 xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg + offset, RESUME_RX0); in xgene_sgmac_init()
298 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) in xgene_sgmac_rxtx() argument
302 data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); in xgene_sgmac_rxtx()
309 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); in xgene_sgmac_rxtx()
312 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_enable() argument
314 xgene_sgmac_rxtx(p, RX_EN, true); in xgene_sgmac_rx_enable()
317 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_enable() argument
319 xgene_sgmac_rxtx(p, TX_EN, true); in xgene_sgmac_tx_enable()
322 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_disable() argument
324 xgene_sgmac_rxtx(p, RX_EN, false); in xgene_sgmac_rx_disable()
327 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_disable() argument
329 xgene_sgmac_rxtx(p, TX_EN, false); in xgene_sgmac_tx_disable()
332 static int xgene_enet_reset(struct xgene_enet_pdata *p) in xgene_enet_reset() argument
334 if (!xgene_ring_mgr_init(p)) in xgene_enet_reset()
337 if (!IS_ERR(p->clk)) { in xgene_enet_reset()
338 clk_prepare_enable(p->clk); in xgene_enet_reset()
339 clk_disable_unprepare(p->clk); in xgene_enet_reset()
340 clk_prepare_enable(p->clk); in xgene_enet_reset()
343 xgene_enet_ecc_init(p); in xgene_enet_reset()
344 xgene_enet_config_ring_if_assoc(p); in xgene_enet_reset()
349 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, in xgene_enet_cle_bypass() argument
354 u32 offset = p->port_id * MAC_OFFSET; in xgene_enet_cle_bypass()
356 if (p->enet_id == XGENE_ENET1) { in xgene_enet_cle_bypass()
365 xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); in xgene_enet_cle_bypass()
369 xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data); in xgene_enet_cle_bypass()
372 static void xgene_enet_shutdown(struct xgene_enet_pdata *p) in xgene_enet_shutdown() argument
374 if (!IS_ERR(p->clk)) in xgene_enet_shutdown()
375 clk_disable_unprepare(p->clk); in xgene_enet_shutdown()
380 struct xgene_enet_pdata *p = container_of(to_delayed_work(work), in xgene_enet_link_state() local
382 struct net_device *ndev = p->ndev; in xgene_enet_link_state()
385 link = xgene_enet_link_status(p); in xgene_enet_link_state()
389 xgene_sgmac_init(p); in xgene_enet_link_state()
390 xgene_sgmac_rx_enable(p); in xgene_enet_link_state()
391 xgene_sgmac_tx_enable(p); in xgene_enet_link_state()
397 xgene_sgmac_rx_disable(p); in xgene_enet_link_state()
398 xgene_sgmac_tx_disable(p); in xgene_enet_link_state()
405 schedule_delayed_work(&p->link_work, poll_interval); in xgene_enet_link_state()