24 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_init()  argument
26 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_init()
27 	u64 addr = ring->dma;  in xgene_enet_ring_init()
29 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {  in xgene_enet_ring_init()
30 		ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);  in xgene_enet_ring_init()
39 	ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize)  in xgene_enet_ring_init()
46 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_set_type()  argument
48 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_set_type()
52 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_ring_set_type()
59 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_set_recombbuf()  argument
61 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_set_recombbuf()
67 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,  in xgene_enet_ring_wr32()  argument
70 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);  in xgene_enet_ring_wr32()
75 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_write_ring_state()  argument
77 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);  in xgene_enet_write_ring_state()
80 	xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);  in xgene_enet_write_ring_state()
82 		xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),  in xgene_enet_write_ring_state()
83 				     ring->state[i]);  in xgene_enet_write_ring_state()
87 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_clr_ring_state()  argument
89 	memset(ring->state, 0, sizeof(ring->state));  in xgene_enet_clr_ring_state()
90 	xgene_enet_write_ring_state(ring);  in xgene_enet_clr_ring_state()
93 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_set_ring_state()  argument
97 	xgene_enet_ring_set_type(ring);  in xgene_enet_set_ring_state()
99 	owner = xgene_enet_ring_owner(ring->id);  in xgene_enet_set_ring_state()
101 		xgene_enet_ring_set_recombbuf(ring);  in xgene_enet_set_ring_state()
103 	xgene_enet_ring_init(ring);  in xgene_enet_set_ring_state()
104 	xgene_enet_write_ring_state(ring);  in xgene_enet_set_ring_state()
107 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)  in xgene_enet_set_ring_id()  argument
112 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)  in xgene_enet_set_ring_id()
115 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_set_ring_id()
117 	ring_id_val = ring->id & GENMASK(9, 0);  in xgene_enet_set_ring_id()
120 	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);  in xgene_enet_set_ring_id()
125 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);  in xgene_enet_set_ring_id()
126 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);  in xgene_enet_set_ring_id()
129 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)  in xgene_enet_clr_desc_ring_id()  argument
133 	ring_id = ring->id | OVERWRITE;  in xgene_enet_clr_desc_ring_id()
134 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);  in xgene_enet_clr_desc_ring_id()
135 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);  in xgene_enet_clr_desc_ring_id()
139 				    struct xgene_enet_desc_ring *ring)  in xgene_enet_setup_ring()  argument
144 	xgene_enet_clr_ring_state(ring);  in xgene_enet_setup_ring()
145 	xgene_enet_set_ring_state(ring);  in xgene_enet_setup_ring()
146 	xgene_enet_set_ring_id(ring);  in xgene_enet_setup_ring()
148 	ring->slots = xgene_enet_get_numslots(ring->id, ring->size);  in xgene_enet_setup_ring()
150 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_setup_ring()
151 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)  in xgene_enet_setup_ring()
152 		return ring;  in xgene_enet_setup_ring()
154 	addr = CSR_VMID0_INTR_MBOX + (4 * (ring->id & RING_BUFNUM_MASK));  in xgene_enet_setup_ring()
155 	xgene_enet_ring_wr32(ring, addr, ring->irq_mbox_dma >> 10);  in xgene_enet_setup_ring()
157 	for (i = 0; i < ring->slots; i++)  in xgene_enet_setup_ring()
158 		xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);  in xgene_enet_setup_ring()
160 	return ring;  in xgene_enet_setup_ring()
163 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)  in xgene_enet_clear_ring()  argument
165 	xgene_enet_clr_desc_ring_id(ring);  in xgene_enet_clear_ring()
166 	xgene_enet_clr_ring_state(ring);  in xgene_enet_clear_ring()
169 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)  in xgene_enet_wr_cmd()  argument
173 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {  in xgene_enet_wr_cmd()
174 		data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) |  in xgene_enet_wr_cmd()
179 	iowrite32(data, ring->cmd);  in xgene_enet_wr_cmd()
182 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_len()  argument
184 	u32 __iomem *cmd_base = ring->cmd_base;  in xgene_enet_ring_len()