29 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {  in xgene_enet_ring_init()
30 		ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);  in xgene_enet_ring_init()
52 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_ring_set_type()
99 	owner = xgene_enet_ring_owner(ring->id);  in xgene_enet_set_ring_state()
112 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)  in xgene_enet_set_ring_id()
115 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_set_ring_id()
117 	ring_id_val = ring->id & GENMASK(9, 0);  in xgene_enet_set_ring_id()
133 	ring_id = ring->id | OVERWRITE;  in xgene_enet_clr_desc_ring_id()
148 	ring->slots = xgene_enet_get_numslots(ring->id, ring->size);  in xgene_enet_setup_ring()
150 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_setup_ring()
151 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)  in xgene_enet_setup_ring()
154 	addr = CSR_VMID0_INTR_MBOX + (4 * (ring->id & RING_BUFNUM_MASK));  in xgene_enet_setup_ring()
173 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {  in xgene_enet_wr_cmd()
174 		data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) |  in xgene_enet_wr_cmd()