25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_init()  argument
27 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_init()
28 	u64 addr = ring->dma;  in xgene_enet_ring_init()
29 	enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;  in xgene_enet_ring_init()
45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_set_type()  argument
47 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_set_type()
51 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_ring_set_type()
62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_set_recombbuf()  argument
64 	u32 *ring_cfg = ring->state;  in xgene_enet_ring_set_recombbuf()
72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,  in xgene_enet_ring_wr32()  argument
75 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);  in xgene_enet_ring_wr32()
80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,  in xgene_enet_ring_rd32()  argument
83 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);  in xgene_enet_ring_rd32()
88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_write_ring_state()  argument
90 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);  in xgene_enet_write_ring_state()
93 	xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);  in xgene_enet_write_ring_state()
95 		xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),  in xgene_enet_write_ring_state()
96 				     ring->state[i]);  in xgene_enet_write_ring_state()
100 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_clr_ring_state()  argument
102 	memset(ring->state, 0, sizeof(ring->state));  in xgene_enet_clr_ring_state()
103 	xgene_enet_write_ring_state(ring);  in xgene_enet_clr_ring_state()
106 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)  in xgene_enet_set_ring_state()  argument
108 	xgene_enet_ring_set_type(ring);  in xgene_enet_set_ring_state()
110 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||  in xgene_enet_set_ring_state()
111 	    xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)  in xgene_enet_set_ring_state()
112 		xgene_enet_ring_set_recombbuf(ring);  in xgene_enet_set_ring_state()
114 	xgene_enet_ring_init(ring);  in xgene_enet_set_ring_state()
115 	xgene_enet_write_ring_state(ring);  in xgene_enet_set_ring_state()
118 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)  in xgene_enet_set_ring_id()  argument
123 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_set_ring_id()
125 	ring_id_val = ring->id & GENMASK(9, 0);  in xgene_enet_set_ring_id()
128 	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);  in xgene_enet_set_ring_id()
133 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);  in xgene_enet_set_ring_id()
134 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);  in xgene_enet_set_ring_id()
137 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)  in xgene_enet_clr_desc_ring_id()  argument
141 	ring_id = ring->id | OVERWRITE;  in xgene_enet_clr_desc_ring_id()
142 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);  in xgene_enet_clr_desc_ring_id()
143 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);  in xgene_enet_clr_desc_ring_id()
147 				    struct xgene_enet_desc_ring *ring)  in xgene_enet_setup_ring()  argument
149 	u32 size = ring->size;  in xgene_enet_setup_ring()
153 	xgene_enet_clr_ring_state(ring);  in xgene_enet_setup_ring()
154 	xgene_enet_set_ring_state(ring);  in xgene_enet_setup_ring()
155 	xgene_enet_set_ring_id(ring);  in xgene_enet_setup_ring()
157 	ring->slots = xgene_enet_get_numslots(ring->id, size);  in xgene_enet_setup_ring()
159 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_setup_ring()
160 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)  in xgene_enet_setup_ring()
161 		return ring;  in xgene_enet_setup_ring()
163 	for (i = 0; i < ring->slots; i++)  in xgene_enet_setup_ring()
164 		xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);  in xgene_enet_setup_ring()
166 	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);  in xgene_enet_setup_ring()
167 	data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));  in xgene_enet_setup_ring()
168 	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);  in xgene_enet_setup_ring()
170 	return ring;  in xgene_enet_setup_ring()
173 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)  in xgene_enet_clear_ring()  argument
178 	is_bufpool = xgene_enet_is_bufpool(ring->id);  in xgene_enet_clear_ring()
179 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)  in xgene_enet_clear_ring()
182 	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);  in xgene_enet_clear_ring()
183 	data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));  in xgene_enet_clear_ring()
184 	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);  in xgene_enet_clear_ring()
187 	xgene_enet_clr_desc_ring_id(ring);  in xgene_enet_clear_ring()
188 	xgene_enet_clr_ring_state(ring);  in xgene_enet_clear_ring()
191 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)  in xgene_enet_wr_cmd()  argument
193 	iowrite32(count, ring->cmd);  in xgene_enet_wr_cmd()
196 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)  in xgene_enet_ring_len()  argument
198 	u32 __iomem *cmd_base = ring->cmd_base;  in xgene_enet_ring_len()
207 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,  in xgene_enet_parse_error()  argument