Lines Matching refs:pdata
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_wr32() local
77 iowrite32(data, pdata->ring_csr_addr + offset); in xgene_enet_ring_wr32()
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_ring_rd32() local
85 *data = ioread32(pdata->ring_csr_addr + offset); in xgene_enet_ring_rd32()
90 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); in xgene_enet_write_ring_state() local
94 for (i = 0; i < pdata->ring_ops->num_ring_config; i++) { in xgene_enet_write_ring_state()
208 struct xgene_enet_pdata *pdata, in xgene_enet_parse_error() argument
211 struct rtnl_link_stats64 *stats = &pdata->stats; in xgene_enet_parse_error()
238 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_csr() argument
241 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_wr_csr()
246 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, in xgene_enet_wr_ring_if() argument
249 void __iomem *addr = pdata->eth_ring_if_addr + offset; in xgene_enet_wr_ring_if()
254 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_diag_csr() argument
257 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_wr_diag_csr()
262 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_mcx_csr() argument
265 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_wr_mcx_csr()
293 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata, in xgene_enet_wr_mcx_mac() argument
298 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_wr_mcx_mac()
299 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; in xgene_enet_wr_mcx_mac()
300 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_wr_mcx_mac()
301 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_wr_mcx_mac()
304 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", in xgene_enet_wr_mcx_mac()
308 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() argument
311 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_rd_csr()
316 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_diag_csr() argument
319 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_rd_diag_csr()
324 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_mcx_csr() argument
327 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_rd_mcx_csr()
355 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata, in xgene_enet_rd_mcx_mac() argument
360 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; in xgene_enet_rd_mcx_mac()
361 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; in xgene_enet_rd_mcx_mac()
362 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; in xgene_enet_rd_mcx_mac()
363 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; in xgene_enet_rd_mcx_mac()
366 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", in xgene_enet_rd_mcx_mac()
370 static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id, in xgene_mii_phy_write() argument
379 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
382 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
385 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); in xgene_mii_phy_write()
389 netdev_err(pdata->ndev, "MII_MGMT write failed\n"); in xgene_mii_phy_write()
396 static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata, in xgene_mii_phy_read() argument
405 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
406 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
409 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); in xgene_mii_phy_read()
413 netdev_err(pdata->ndev, "MII_MGMT read failed\n"); in xgene_mii_phy_read()
417 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data); in xgene_mii_phy_read()
418 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
423 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata) in xgene_gmac_set_mac_addr() argument
426 u8 *dev_addr = pdata->ndev->dev_addr; in xgene_gmac_set_mac_addr()
432 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0); in xgene_gmac_set_mac_addr()
433 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1); in xgene_gmac_set_mac_addr()
436 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) in xgene_enet_ecc_init() argument
438 struct net_device *ndev = pdata->ndev; in xgene_enet_ecc_init()
442 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); in xgene_enet_ecc_init()
445 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); in xgene_enet_ecc_init()
456 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata) in xgene_gmac_reset() argument
458 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_gmac_reset()
459 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0); in xgene_gmac_reset()
462 static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata) in xgene_enet_configure_clock() argument
464 struct device *dev = &pdata->pdev->dev; in xgene_enet_configure_clock()
467 struct clk *parent = clk_get_parent(pdata->clk); in xgene_enet_configure_clock()
469 switch (pdata->phy_speed) { in xgene_enet_configure_clock()
483 switch (pdata->phy_speed) { in xgene_enet_configure_clock()
501 static void xgene_gmac_init(struct xgene_enet_pdata *pdata) in xgene_gmac_init() argument
503 struct device *dev = &pdata->pdev->dev; in xgene_gmac_init()
508 xgene_gmac_reset(pdata); in xgene_gmac_init()
510 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0); in xgene_gmac_init()
511 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2); in xgene_gmac_init()
512 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2); in xgene_gmac_init()
513 xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl); in xgene_gmac_init()
514 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_init()
516 switch (pdata->phy_speed) { in xgene_gmac_init()
539 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay); in xgene_gmac_init()
540 CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay); in xgene_gmac_init()
544 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_init()
546 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); in xgene_gmac_init()
551 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2); in xgene_gmac_init()
552 xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); in xgene_gmac_init()
554 xgene_gmac_set_mac_addr(pdata); in xgene_gmac_init()
557 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value); in xgene_gmac_init()
559 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value); in xgene_gmac_init()
562 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
564 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); in xgene_gmac_init()
567 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); in xgene_gmac_init()
568 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); in xgene_gmac_init()
569 xgene_enet_configure_clock(pdata); in xgene_gmac_init()
572 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); in xgene_gmac_init()
574 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0); in xgene_gmac_init()
575 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2); in xgene_gmac_init()
577 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value); in xgene_gmac_init()
581 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value); in xgene_gmac_init()
583 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); in xgene_gmac_init()
586 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) in xgene_enet_config_ring_if_assoc() argument
590 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
591 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
592 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
593 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
596 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, in xgene_enet_cle_bypass() argument
604 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
607 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); in xgene_enet_cle_bypass()
609 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()
612 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb); in xgene_enet_cle_bypass()
615 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_enable() argument
619 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_rx_enable()
620 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN); in xgene_gmac_rx_enable()
623 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_enable() argument
627 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_tx_enable()
628 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN); in xgene_gmac_tx_enable()
631 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_rx_disable() argument
635 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_rx_disable()
636 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN); in xgene_gmac_rx_disable()
639 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata) in xgene_gmac_tx_disable() argument
643 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); in xgene_gmac_tx_disable()
644 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN); in xgene_gmac_tx_disable()
658 static int xgene_enet_reset(struct xgene_enet_pdata *pdata) in xgene_enet_reset() argument
662 if (!xgene_ring_mgr_init(pdata)) in xgene_enet_reset()
665 if (!IS_ERR(pdata->clk)) { in xgene_enet_reset()
666 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
667 clk_disable_unprepare(pdata->clk); in xgene_enet_reset()
668 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
669 xgene_enet_ecc_init(pdata); in xgene_enet_reset()
671 xgene_enet_config_ring_if_assoc(pdata); in xgene_enet_reset()
674 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val); in xgene_enet_reset()
677 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val); in xgene_enet_reset()
682 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) in xgene_gport_shutdown() argument
684 if (!IS_ERR(pdata->clk)) in xgene_gport_shutdown()
685 clk_disable_unprepare(pdata->clk); in xgene_gport_shutdown()
690 struct xgene_enet_pdata *pdata = bus->priv; in xgene_enet_mdio_read() local
693 val = xgene_mii_phy_read(pdata, mii_id, regnum); in xgene_enet_mdio_read()
694 netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n", in xgene_enet_mdio_read()
703 struct xgene_enet_pdata *pdata = bus->priv; in xgene_enet_mdio_write() local
705 netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n", in xgene_enet_mdio_write()
707 return xgene_mii_phy_write(pdata, mii_id, regnum, val); in xgene_enet_mdio_write()
712 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_adjust_link() local
713 struct phy_device *phydev = pdata->phy_dev; in xgene_enet_adjust_link()
716 if (pdata->phy_speed != phydev->speed) { in xgene_enet_adjust_link()
717 pdata->phy_speed = phydev->speed; in xgene_enet_adjust_link()
718 xgene_gmac_init(pdata); in xgene_enet_adjust_link()
719 xgene_gmac_rx_enable(pdata); in xgene_enet_adjust_link()
720 xgene_gmac_tx_enable(pdata); in xgene_enet_adjust_link()
724 xgene_gmac_rx_disable(pdata); in xgene_enet_adjust_link()
725 xgene_gmac_tx_disable(pdata); in xgene_enet_adjust_link()
726 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_adjust_link()
733 struct xgene_enet_pdata *pdata = netdev_priv(ndev); in xgene_enet_phy_connect() local
736 struct device *dev = &pdata->pdev->dev; in xgene_enet_phy_connect()
746 0, pdata->phy_mode); in xgene_enet_phy_connect()
752 pdata->phy_dev = phy_dev; in xgene_enet_phy_connect()
754 phy_dev = pdata->phy_dev; in xgene_enet_phy_connect()
758 pdata->phy_mode)) { in xgene_enet_phy_connect()
764 pdata->phy_speed = SPEED_UNKNOWN; in xgene_enet_phy_connect()
773 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata, in xgene_mdiobus_register() argument
776 struct device *dev = &pdata->pdev->dev; in xgene_mdiobus_register()
777 struct net_device *ndev = pdata->ndev; in xgene_mdiobus_register()
823 pdata->phy_dev = phy; in xgene_mdiobus_register()
828 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_config() argument
830 struct net_device *ndev = pdata->ndev; in xgene_enet_mdio_config()
844 mdio_bus->priv = pdata; in xgene_enet_mdio_config()
847 ret = xgene_mdiobus_register(pdata, mdio_bus); in xgene_enet_mdio_config()
853 pdata->mdio_bus = mdio_bus; in xgene_enet_mdio_config()
857 xgene_enet_mdio_remove(pdata); in xgene_enet_mdio_config()
862 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) in xgene_enet_mdio_remove() argument
864 if (pdata->phy_dev) in xgene_enet_mdio_remove()
865 phy_disconnect(pdata->phy_dev); in xgene_enet_mdio_remove()
867 mdiobus_unregister(pdata->mdio_bus); in xgene_enet_mdio_remove()
868 mdiobus_free(pdata->mdio_bus); in xgene_enet_mdio_remove()
869 pdata->mdio_bus = NULL; in xgene_enet_mdio_remove()