Lines Matching refs:BIT

55 #define SGDMA_STATUS_ERR		BIT(0)
56 #define SGDMA_STATUS_LENGTH_ERR		BIT(1)
57 #define SGDMA_STATUS_CRC_ERR		BIT(2)
58 #define SGDMA_STATUS_TRUNC_ERR		BIT(3)
59 #define SGDMA_STATUS_PHY_ERR		BIT(4)
60 #define SGDMA_STATUS_COLL_ERR		BIT(5)
61 #define SGDMA_STATUS_EOP		BIT(7)
63 #define SGDMA_CONTROL_EOP		BIT(0)
64 #define SGDMA_CONTROL_RD_FIXED		BIT(1)
65 #define SGDMA_CONTROL_WR_FIXED		BIT(2)
69 #define SGDMA_CONTROL_HW_OWNED		BIT(7)
108 #define SGDMA_STSREG_ERR	BIT(0) /* Error */
109 #define SGDMA_STSREG_EOP	BIT(1) /* EOP */
110 #define SGDMA_STSREG_DESCRIP	BIT(2) /* Descriptor completed */
111 #define SGDMA_STSREG_CHAIN	BIT(3) /* Chain completed */
112 #define SGDMA_STSREG_BUSY	BIT(4) /* Controller busy */
114 #define SGDMA_CTRLREG_IOE	BIT(0) /* Interrupt on error */
115 #define SGDMA_CTRLREG_IOEOP	BIT(1) /* Interrupt on EOP */
116 #define SGDMA_CTRLREG_IDESCRIP	BIT(2) /* Interrupt after every descriptor */
117 #define SGDMA_CTRLREG_ILASTD	BIT(3) /* Interrupt after last descriptor */
118 #define SGDMA_CTRLREG_INTEN	BIT(4) /* Global Interrupt enable */
119 #define SGDMA_CTRLREG_START	BIT(5) /* starts descriptor processing */
120 #define SGDMA_CTRLREG_STOPERR	BIT(6) /* stop on dma error */
121 #define SGDMA_CTRLREG_INTMAX	BIT(7) /* Interrupt on max descriptors */
122 #define SGDMA_CTRLREG_RESET	BIT(16)/* Software reset */
123 #define SGDMA_CTRLREG_COBHW	BIT(17)/* Clears owned by hardware */
124 #define SGDMA_CTRLREG_POLL	BIT(18)/* enables descriptor polling mode */
125 #define SGDMA_CTRLREG_CLRINT	BIT(31)/* Clears interrupt */