757 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
760 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
775 	csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
778 		csr = readl(&adapter->regs->rxdma.csr);  in et131x_rx_dma_disable()
873 	ctl = readl(&adapter->regs->txmac.ctl);  in et1310_config_mac_regs2()
874 	cfg1 = readl(&mac->cfg1);  in et1310_config_mac_regs2()
875 	cfg2 = readl(&mac->cfg2);  in et1310_config_mac_regs2()
876 	ifctrl = readl(&mac->if_ctrl);  in et1310_config_mac_regs2()
920 		cfg1 = readl(&mac->cfg1);  in et1310_config_mac_regs2()
940 	u32 pmcsr = readl(&adapter->regs->global.pm_csr);  in et1310_in_phy_coma()
986 	pm_csr = readl(&adapter->regs->global.pm_csr);  in et1310_setup_device_for_multicast()
1027 	pm_csr = readl(&adapter->regs->global.pm_csr);  in et1310_setup_device_for_unicast()
1185 	mii_addr = readl(&mac->mii_mgmt_addr);  in et131x_phy_mii_read()
1186 	mii_cmd = readl(&mac->mii_mgmt_cmd);  in et131x_phy_mii_read()
1199 		mii_indicator = readl(&mac->mii_mgmt_indicator);  in et131x_phy_mii_read()
1216 	*value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;  in et131x_phy_mii_read()
1254 	mii_addr = readl(&mac->mii_mgmt_addr);  in et131x_mii_write()
1255 	mii_cmd = readl(&mac->mii_mgmt_cmd);  in et131x_mii_write()
1269 		mii_indicator = readl(&mac->mii_mgmt_indicator);  in et131x_mii_write()
1281 			 readl(&mac->mii_mgmt_cmd));  in et131x_mii_write()
1349 	stats->tx_collisions	       += readl(&macstat->tx_total_collisions);  in et1310_update_macstat_host_counters()
1350 	stats->tx_first_collisions     += readl(&macstat->tx_single_collisions);  in et1310_update_macstat_host_counters()
1351 	stats->tx_deferred	       += readl(&macstat->tx_deferred);  in et1310_update_macstat_host_counters()
1353 				readl(&macstat->tx_multiple_collisions);  in et1310_update_macstat_host_counters()
1354 	stats->tx_late_collisions      += readl(&macstat->tx_late_collisions);  in et1310_update_macstat_host_counters()
1355 	stats->tx_underflows	       += readl(&macstat->tx_undersize_frames);  in et1310_update_macstat_host_counters()
1356 	stats->tx_max_pkt_errs	       += readl(&macstat->tx_oversize_frames);  in et1310_update_macstat_host_counters()
1358 	stats->rx_align_errs        += readl(&macstat->rx_align_errs);  in et1310_update_macstat_host_counters()
1359 	stats->rx_crc_errs          += readl(&macstat->rx_code_errs);  in et1310_update_macstat_host_counters()
1360 	stats->rcvd_pkts_dropped    += readl(&macstat->rx_drops);  in et1310_update_macstat_host_counters()
1361 	stats->rx_overflows         += readl(&macstat->rx_oversize_packets);  in et1310_update_macstat_host_counters()
1362 	stats->rx_code_violations   += readl(&macstat->rx_fcs_errs);  in et1310_update_macstat_host_counters()
1363 	stats->rx_length_errs       += readl(&macstat->rx_frame_len_errs);  in et1310_update_macstat_host_counters()
1364 	stats->rx_other_errs        += readl(&macstat->rx_fragment_packets);  in et1310_update_macstat_host_counters()
1381 	carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);  in et1310_handle_macstat_interrupt()
1382 	carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);  in et1310_handle_macstat_interrupt()
1563 	psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;  in et131x_config_rx_dma_regs()
1787 	u32 pmcsr = readl(&adapter->regs->global.pm_csr);  in et1310_enable_phy_coma()
1808 	pmcsr = readl(&adapter->regs->global.pm_csr);  in et1310_disable_phy_coma()
2746 	serviced = readl(&adapter->regs->txdma.new_service_complete);  in et131x_handle_send_pkts()
2895 	regs_buff[num++] = readl(&aregs->global.txq_start_addr);  in et131x_get_regs()
2896 	regs_buff[num++] = readl(&aregs->global.txq_end_addr);  in et131x_get_regs()
2897 	regs_buff[num++] = readl(&aregs->global.rxq_start_addr);  in et131x_get_regs()
2898 	regs_buff[num++] = readl(&aregs->global.rxq_end_addr);  in et131x_get_regs()
2899 	regs_buff[num++] = readl(&aregs->global.pm_csr);  in et131x_get_regs()
2901 	regs_buff[num++] = readl(&aregs->global.int_mask);  in et131x_get_regs()
2902 	regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);  in et131x_get_regs()
2903 	regs_buff[num++] = readl(&aregs->global.int_status_alias);  in et131x_get_regs()
2904 	regs_buff[num++] = readl(&aregs->global.sw_reset);  in et131x_get_regs()
2905 	regs_buff[num++] = readl(&aregs->global.slv_timer);  in et131x_get_regs()
2906 	regs_buff[num++] = readl(&aregs->global.msi_config);  in et131x_get_regs()
2907 	regs_buff[num++] = readl(&aregs->global.loopback);  in et131x_get_regs()
2908 	regs_buff[num++] = readl(&aregs->global.watchdog_timer);  in et131x_get_regs()
2911 	regs_buff[num++] = readl(&aregs->txdma.csr);  in et131x_get_regs()
2912 	regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);  in et131x_get_regs()
2913 	regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);  in et131x_get_regs()
2914 	regs_buff[num++] = readl(&aregs->txdma.pr_num_des);  in et131x_get_regs()
2915 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);  in et131x_get_regs()
2916 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);  in et131x_get_regs()
2917 	regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);  in et131x_get_regs()
2918 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);  in et131x_get_regs()
2919 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);  in et131x_get_regs()
2920 	regs_buff[num++] = readl(&aregs->txdma.service_request);  in et131x_get_regs()
2921 	regs_buff[num++] = readl(&aregs->txdma.service_complete);  in et131x_get_regs()
2922 	regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);  in et131x_get_regs()
2923 	regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);  in et131x_get_regs()
2924 	regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);  in et131x_get_regs()
2925 	regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);  in et131x_get_regs()
2926 	regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);  in et131x_get_regs()
2927 	regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);  in et131x_get_regs()
2928 	regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);  in et131x_get_regs()
2929 	regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);  in et131x_get_regs()
2930 	regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);  in et131x_get_regs()
2931 	regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);  in et131x_get_regs()
2932 	regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);  in et131x_get_regs()
2933 	regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);  in et131x_get_regs()
2934 	regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);  in et131x_get_regs()
2935 	regs_buff[num++] = readl(&aregs->txdma.new_service_complete);  in et131x_get_regs()
2936 	regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);  in et131x_get_regs()
2939 	regs_buff[num++] = readl(&aregs->rxdma.csr);  in et131x_get_regs()
2940 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);  in et131x_get_regs()
2941 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);  in et131x_get_regs()
2942 	regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);  in et131x_get_regs()
2943 	regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);  in et131x_get_regs()
2944 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);  in et131x_get_regs()
2945 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);  in et131x_get_regs()
2946 	regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);  in et131x_get_regs()
2947 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);  in et131x_get_regs()
2948 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);  in et131x_get_regs()
2949 	regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);  in et131x_get_regs()
2950 	regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);  in et131x_get_regs()
2951 	regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);  in et131x_get_regs()
2952 	regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);  in et131x_get_regs()
2953 	regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);  in et131x_get_regs()
2954 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);  in et131x_get_regs()
2955 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);  in et131x_get_regs()
2956 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);  in et131x_get_regs()
2957 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);  in et131x_get_regs()
2958 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);  in et131x_get_regs()
2959 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);  in et131x_get_regs()
2960 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);  in et131x_get_regs()
2961 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);  in et131x_get_regs()
2962 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);  in et131x_get_regs()
2963 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);  in et131x_get_regs()
2964 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);  in et131x_get_regs()
2965 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);  in et131x_get_regs()
2966 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);  in et131x_get_regs()
2967 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);  in et131x_get_regs()
3412 	status = readl(&adapter->regs->global.int_status);  in et131x_isr()
3454 		u32 txdma_err = readl(&iomem->txdma.tx_dma_error);  in et131x_isr()
3483 			pm_csr = readl(&iomem->global.pm_csr);  in et131x_isr()
3518 			 readl(&iomem->txmac.tx_test));  in et131x_isr()
3531 		u32 err = readl(&iomem->txmac.err);  in et131x_isr()
3556 			 readl(&iomem->rxmac.err_reg));  in et131x_isr()
3560 			 readl(&iomem->rxmac.ctrl),  in et131x_isr()
3561 			 readl(&iomem->rxmac.rxq_diag));  in et131x_isr()
3705 	ctrl = readl(&adapter->regs->rxmac.ctrl);  in et131x_set_packet_filter()
3706 	pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);  in et131x_set_packet_filter()