2822 	u32 num = 0;  in et131x_get_regs()  local
2832 	regs_buff[num++] = tmp;  in et131x_get_regs()
2834 	regs_buff[num++] = tmp;  in et131x_get_regs()
2836 	regs_buff[num++] = tmp;  in et131x_get_regs()
2838 	regs_buff[num++] = tmp;  in et131x_get_regs()
2840 	regs_buff[num++] = tmp;  in et131x_get_regs()
2842 	regs_buff[num++] = tmp;  in et131x_get_regs()
2844 	regs_buff[num++] = tmp;  in et131x_get_regs()
2847 	regs_buff[num++] = tmp;  in et131x_get_regs()
2850 	regs_buff[num++] = tmp;  in et131x_get_regs()
2852 	regs_buff[num++] = tmp;  in et131x_get_regs()
2854 	regs_buff[num++] = tmp;  in et131x_get_regs()
2856 	regs_buff[num++] = tmp;  in et131x_get_regs()
2858 	regs_buff[num++] = tmp;  in et131x_get_regs()
2860 	regs_buff[num++] = tmp;  in et131x_get_regs()
2862 	regs_buff[num++] = tmp;  in et131x_get_regs()
2864 	regs_buff[num++] = tmp;  in et131x_get_regs()
2867 	regs_buff[num++] = tmp;  in et131x_get_regs()
2869 	regs_buff[num++] = tmp;  in et131x_get_regs()
2871 	regs_buff[num++] = tmp;  in et131x_get_regs()
2873 	regs_buff[num++] = tmp;  in et131x_get_regs()
2875 	regs_buff[num++] = tmp;  in et131x_get_regs()
2878 	regs_buff[num++] = tmp;  in et131x_get_regs()
2880 	regs_buff[num++] = tmp;  in et131x_get_regs()
2882 	regs_buff[num++] = tmp;  in et131x_get_regs()
2884 	regs_buff[num++] = tmp;  in et131x_get_regs()
2886 	regs_buff[num++] = tmp;  in et131x_get_regs()
2888 	regs_buff[num++] = tmp;  in et131x_get_regs()
2890 	regs_buff[num++] = tmp;  in et131x_get_regs()
2892 	regs_buff[num++] = tmp;  in et131x_get_regs()
2895 	regs_buff[num++] = readl(&aregs->global.txq_start_addr);  in et131x_get_regs()
2896 	regs_buff[num++] = readl(&aregs->global.txq_end_addr);  in et131x_get_regs()
2897 	regs_buff[num++] = readl(&aregs->global.rxq_start_addr);  in et131x_get_regs()
2898 	regs_buff[num++] = readl(&aregs->global.rxq_end_addr);  in et131x_get_regs()
2899 	regs_buff[num++] = readl(&aregs->global.pm_csr);  in et131x_get_regs()
2900 	regs_buff[num++] = adapter->stats.interrupt_status;  in et131x_get_regs()
2901 	regs_buff[num++] = readl(&aregs->global.int_mask);  in et131x_get_regs()
2902 	regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);  in et131x_get_regs()
2903 	regs_buff[num++] = readl(&aregs->global.int_status_alias);  in et131x_get_regs()
2904 	regs_buff[num++] = readl(&aregs->global.sw_reset);  in et131x_get_regs()
2905 	regs_buff[num++] = readl(&aregs->global.slv_timer);  in et131x_get_regs()
2906 	regs_buff[num++] = readl(&aregs->global.msi_config);  in et131x_get_regs()
2907 	regs_buff[num++] = readl(&aregs->global.loopback);  in et131x_get_regs()
2908 	regs_buff[num++] = readl(&aregs->global.watchdog_timer);  in et131x_get_regs()
2911 	regs_buff[num++] = readl(&aregs->txdma.csr);  in et131x_get_regs()
2912 	regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);  in et131x_get_regs()
2913 	regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);  in et131x_get_regs()
2914 	regs_buff[num++] = readl(&aregs->txdma.pr_num_des);  in et131x_get_regs()
2915 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);  in et131x_get_regs()
2916 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);  in et131x_get_regs()
2917 	regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);  in et131x_get_regs()
2918 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);  in et131x_get_regs()
2919 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);  in et131x_get_regs()
2920 	regs_buff[num++] = readl(&aregs->txdma.service_request);  in et131x_get_regs()
2921 	regs_buff[num++] = readl(&aregs->txdma.service_complete);  in et131x_get_regs()
2922 	regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);  in et131x_get_regs()
2923 	regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);  in et131x_get_regs()
2924 	regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);  in et131x_get_regs()
2925 	regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);  in et131x_get_regs()
2926 	regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);  in et131x_get_regs()
2927 	regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);  in et131x_get_regs()
2928 	regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);  in et131x_get_regs()
2929 	regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);  in et131x_get_regs()
2930 	regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);  in et131x_get_regs()
2931 	regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);  in et131x_get_regs()
2932 	regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);  in et131x_get_regs()
2933 	regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);  in et131x_get_regs()
2934 	regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);  in et131x_get_regs()
2935 	regs_buff[num++] = readl(&aregs->txdma.new_service_complete);  in et131x_get_regs()
2936 	regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);  in et131x_get_regs()
2939 	regs_buff[num++] = readl(&aregs->rxdma.csr);  in et131x_get_regs()
2940 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);  in et131x_get_regs()
2941 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);  in et131x_get_regs()
2942 	regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);  in et131x_get_regs()
2943 	regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);  in et131x_get_regs()
2944 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);  in et131x_get_regs()
2945 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);  in et131x_get_regs()
2946 	regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);  in et131x_get_regs()
2947 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);  in et131x_get_regs()
2948 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);  in et131x_get_regs()
2949 	regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);  in et131x_get_regs()
2950 	regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);  in et131x_get_regs()
2951 	regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);  in et131x_get_regs()
2952 	regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);  in et131x_get_regs()
2953 	regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);  in et131x_get_regs()
2954 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);  in et131x_get_regs()
2955 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);  in et131x_get_regs()
2956 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);  in et131x_get_regs()
2957 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);  in et131x_get_regs()
2958 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);  in et131x_get_regs()
2959 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);  in et131x_get_regs()
2960 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);  in et131x_get_regs()
2961 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);  in et131x_get_regs()
2962 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);  in et131x_get_regs()
2963 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);  in et131x_get_regs()
2964 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);  in et131x_get_regs()
2965 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);  in et131x_get_regs()
2966 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);  in et131x_get_regs()
2967 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);  in et131x_get_regs()