265 		outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, ioaddr + E8390_CMD);  in ne2k_pci_init_one()
267 		outb(0xff, ioaddr + 0x0d);  in ne2k_pci_init_one()
268 		outb(E8390_NODMA+E8390_PAGE0, ioaddr + E8390_CMD);  in ne2k_pci_init_one()
271 			outb(reg0, ioaddr);  in ne2k_pci_init_one()
272 			outb(regd, ioaddr + 0x0d);	/* Restore the old values. */  in ne2k_pci_init_one()
293 		outb(inb(ioaddr + NE_RESET), ioaddr + NE_RESET);  in ne2k_pci_init_one()
306 		outb(0xff, ioaddr + EN0_ISR);		/* Ack all intr. */  in ne2k_pci_init_one()
330 			outb(program_seq[i].value, ioaddr + program_seq[i].offset);  in ne2k_pci_init_one()
344 	outb(0x49, ioaddr + EN0_DCFG);  in ne2k_pci_init_one()
407 	outb(0xC0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 3 */  in set_realtek_fdx()
408 	outb(0xC0, ioaddr + 0x01); /* Enable writes to CONFIG3 */  in set_realtek_fdx()
409 	outb(0x40, ioaddr + 0x06); /* Enable full duplex */  in set_realtek_fdx()
410 	outb(0x00, ioaddr + 0x01); /* Disable writes to CONFIG3 */  in set_realtek_fdx()
411 	outb(E8390_PAGE0 + E8390_NODMA, ioaddr + NE_CMD); /* Page 0 */  in set_realtek_fdx()
419 	outb(inb(ioaddr + 0x20) | 0x80, ioaddr + 0x20);  in set_holtek_fdx()
463 	outb(inb(NE_BASE + NE_RESET), NE_BASE + NE_RESET);  in ne2k_pci_reset_8390()
474 	outb(ENISR_RESET, NE_BASE + EN0_ISR);	/* Ack intr. */  in ne2k_pci_reset_8390()
495 	outb(E8390_NODMA+E8390_PAGE0+E8390_START, nic_base+ NE_CMD);  in ne2k_pci_get_8390_hdr()
496 	outb(sizeof(struct e8390_pkt_hdr), nic_base + EN0_RCNTLO);  in ne2k_pci_get_8390_hdr()
497 	outb(0, nic_base + EN0_RCNTHI);  in ne2k_pci_get_8390_hdr()
498 	outb(0, nic_base + EN0_RSARLO);		/* On page boundary */  in ne2k_pci_get_8390_hdr()
499 	outb(ring_page, nic_base + EN0_RSARHI);  in ne2k_pci_get_8390_hdr()
500 	outb(E8390_RREAD+E8390_START, nic_base + NE_CMD);  in ne2k_pci_get_8390_hdr()
509 	outb(ENISR_RDC, nic_base + EN0_ISR);	/* Ack intr. */  in ne2k_pci_get_8390_hdr()
534 	outb(E8390_NODMA+E8390_PAGE0+E8390_START, nic_base+ NE_CMD);  in ne2k_pci_block_input()
535 	outb(count & 0xff, nic_base + EN0_RCNTLO);  in ne2k_pci_block_input()
536 	outb(count >> 8, nic_base + EN0_RCNTHI);  in ne2k_pci_block_input()
537 	outb(ring_offset & 0xff, nic_base + EN0_RSARLO);  in ne2k_pci_block_input()
538 	outb(ring_offset >> 8, nic_base + EN0_RSARHI);  in ne2k_pci_block_input()
539 	outb(E8390_RREAD+E8390_START, nic_base + NE_CMD);  in ne2k_pci_block_input()
561 	outb(ENISR_RDC, nic_base + EN0_ISR);	/* Ack intr. */  in ne2k_pci_block_input()
588 	outb(E8390_PAGE0+E8390_START+E8390_NODMA, nic_base + NE_CMD);  in ne2k_pci_block_output()
595 	outb(0x42, nic_base + EN0_RCNTLO);  in ne2k_pci_block_output()
596 	outb(0x00, nic_base + EN0_RCNTHI);  in ne2k_pci_block_output()
597 	outb(0x42, nic_base + EN0_RSARLO);  in ne2k_pci_block_output()
598 	outb(0x00, nic_base + EN0_RSARHI);  in ne2k_pci_block_output()
599 	outb(E8390_RREAD+E8390_START, nic_base + NE_CMD);  in ne2k_pci_block_output()
601 	outb(ENISR_RDC, nic_base + EN0_ISR);  in ne2k_pci_block_output()
604 	outb(count & 0xff, nic_base + EN0_RCNTLO);  in ne2k_pci_block_output()
605 	outb(count >> 8,   nic_base + EN0_RCNTHI);  in ne2k_pci_block_output()
606 	outb(0x00, nic_base + EN0_RSARLO);  in ne2k_pci_block_output()
607 	outb(start_page, nic_base + EN0_RSARHI);  in ne2k_pci_block_output()
608 	outb(E8390_RWRITE+E8390_START, nic_base + NE_CMD);  in ne2k_pci_block_output()
634 	outb(ENISR_RDC, nic_base + EN0_ISR);	/* Ack intr. */  in ne2k_pci_block_output()