465 	IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,  enumerator
1717 	vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |  in vortex_up()
1723 	iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,  in vortex_up()
1910 	if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {  in vortex_tx_timeout()
2288 	if ((status & IntLatch) == 0)  in vortex_interrupt()
2363 			} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);  in vortex_interrupt()
2369 		iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);  in vortex_interrupt()
2370 	} while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));  in vortex_interrupt()
2414 	if ((status & IntLatch) == 0)  in boomerang_interrupt()
2502 			} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);  in boomerang_interrupt()
2508 		iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);  in boomerang_interrupt()
2512 	} while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);  in boomerang_interrupt()