228 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)  in get_tx_head_mb()  argument
230 	return priv->tx_head & HECC_TX_MB_MASK;  in get_tx_head_mb()
233 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)  in get_tx_tail_mb()  argument
235 	return priv->tx_tail & HECC_TX_MB_MASK;  in get_tx_tail_mb()
238 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)  in get_tx_head_prio()  argument
240 	return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;  in get_tx_head_prio()
243 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)  in hecc_write_lam()  argument
245 	__raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);  in hecc_write_lam()
248 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,  in hecc_write_mbx()  argument
251 	__raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +  in hecc_write_mbx()
255 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)  in hecc_read_mbx()  argument
257 	return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +  in hecc_read_mbx()
261 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)  in hecc_write()  argument
263 	__raw_writel(val, priv->base + reg);  in hecc_write()
266 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)  in hecc_read()  argument
268 	return __raw_readl(priv->base + reg);  in hecc_read()
271 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,  in hecc_set_bit()  argument
274 	hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);  in hecc_set_bit()
277 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,  in hecc_clear_bit()  argument
280 	hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);  in hecc_clear_bit()
283 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)  in hecc_get_bit()  argument
285 	return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;  in hecc_get_bit()
288 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)  in ti_hecc_set_btc()  argument
290 	struct can_bittiming *bit_timing = &priv->can.bittiming;  in ti_hecc_set_btc()
296 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {  in ti_hecc_set_btc()
300 			netdev_warn(priv->ndev, "WARN: Triple"  in ti_hecc_set_btc()
308 	hecc_write(priv, HECC_CANBTC, can_btc);  in ti_hecc_set_btc()
309 	netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);  in ti_hecc_set_btc()
314 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,  in ti_hecc_transceiver_switch()  argument
317 	if (priv->transceiver_switch)  in ti_hecc_transceiver_switch()
318 		priv->transceiver_switch(on);  in ti_hecc_transceiver_switch()
324 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_reset()  local
327 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);  in ti_hecc_reset()
330 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);  in ti_hecc_reset()
338 	while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {  in ti_hecc_reset()
348 	ti_hecc_set_btc(priv);  in ti_hecc_reset()
351 	hecc_write(priv, HECC_CANMC, 0);  in ti_hecc_reset()
363 	while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {  in ti_hecc_reset()
369 	hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);  in ti_hecc_reset()
370 	hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);  in ti_hecc_reset()
373 	hecc_write(priv, HECC_CANTA, HECC_SET_REG);  in ti_hecc_reset()
374 	hecc_write(priv, HECC_CANRMP, HECC_SET_REG);  in ti_hecc_reset()
375 	hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);  in ti_hecc_reset()
376 	hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);  in ti_hecc_reset()
377 	hecc_write(priv, HECC_CANME, 0);  in ti_hecc_reset()
378 	hecc_write(priv, HECC_CANMD, 0);  in ti_hecc_reset()
381 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);  in ti_hecc_reset()
386 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_start()  local
392 	priv->tx_head = priv->tx_tail = HECC_TX_MASK;  in ti_hecc_start()
393 	priv->rx_next = HECC_RX_FIRST_MBOX;  in ti_hecc_start()
396 	hecc_write(priv, HECC_CANGAM, HECC_SET_REG);  in ti_hecc_start()
402 		hecc_clear_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_start()
403 		hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);  in ti_hecc_start()
404 		hecc_write_lam(priv, mbxno, HECC_SET_REG);  in ti_hecc_start()
405 		hecc_set_bit(priv, HECC_CANMD, mbx_mask);  in ti_hecc_start()
406 		hecc_set_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_start()
407 		hecc_set_bit(priv, HECC_CANMIM, mbx_mask);  in ti_hecc_start()
411 	hecc_write(priv, HECC_CANOPC, HECC_SET_REG);  in ti_hecc_start()
412 	if (priv->int_line) {  in ti_hecc_start()
413 		hecc_write(priv, HECC_CANMIL, HECC_SET_REG);  in ti_hecc_start()
414 		hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |  in ti_hecc_start()
417 		hecc_write(priv, HECC_CANMIL, 0);  in ti_hecc_start()
418 		hecc_write(priv, HECC_CANGIM,  in ti_hecc_start()
421 	priv->can.state = CAN_STATE_ERROR_ACTIVE;  in ti_hecc_start()
426 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_stop()  local
429 	hecc_write(priv, HECC_CANGIM, 0);  in ti_hecc_stop()
430 	hecc_write(priv, HECC_CANMIM, 0);  in ti_hecc_stop()
431 	hecc_write(priv, HECC_CANME, 0);  in ti_hecc_stop()
432 	priv->can.state = CAN_STATE_STOPPED;  in ti_hecc_stop()
455 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_get_berr_counter()  local
457 	bec->txerr = hecc_read(priv, HECC_CANTEC);  in ti_hecc_get_berr_counter()
458 	bec->rxerr = hecc_read(priv, HECC_CANREC);  in ti_hecc_get_berr_counter()
487 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_xmit()  local
495 	mbxno = get_tx_head_mb(priv);  in ti_hecc_xmit()
497 	spin_lock_irqsave(&priv->mbx_lock, flags);  in ti_hecc_xmit()
498 	if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {  in ti_hecc_xmit()
499 		spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_xmit()
501 		netdev_err(priv->ndev,  in ti_hecc_xmit()
503 			priv->tx_head, priv->tx_tail);  in ti_hecc_xmit()
506 	spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_xmit()
509 	data = cf->can_dlc | (get_tx_head_prio(priv) << 8);  in ti_hecc_xmit()
512 	hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);  in ti_hecc_xmit()
518 	hecc_write_mbx(priv, mbxno, HECC_CANMID, data);  in ti_hecc_xmit()
519 	hecc_write_mbx(priv, mbxno, HECC_CANMDL,  in ti_hecc_xmit()
522 		hecc_write_mbx(priv, mbxno, HECC_CANMDH,  in ti_hecc_xmit()
528 	spin_lock_irqsave(&priv->mbx_lock, flags);  in ti_hecc_xmit()
529 	--priv->tx_head;  in ti_hecc_xmit()
530 	if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||  in ti_hecc_xmit()
531 		(priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {  in ti_hecc_xmit()
534 	hecc_set_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_xmit()
535 	spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_xmit()
537 	hecc_clear_bit(priv, HECC_CANMD, mbx_mask);  in ti_hecc_xmit()
538 	hecc_set_bit(priv, HECC_CANMIM, mbx_mask);  in ti_hecc_xmit()
539 	hecc_write(priv, HECC_CANTRS, mbx_mask);  in ti_hecc_xmit()
544 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)  in ti_hecc_rx_pkt()  argument
546 	struct net_device_stats *stats = &priv->ndev->stats;  in ti_hecc_rx_pkt()
552 	skb = alloc_can_skb(priv->ndev, &cf);  in ti_hecc_rx_pkt()
555 			netdev_err(priv->ndev,  in ti_hecc_rx_pkt()
561 	data = hecc_read_mbx(priv, mbxno, HECC_CANMID);  in ti_hecc_rx_pkt()
566 	data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);  in ti_hecc_rx_pkt()
570 	data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);  in ti_hecc_rx_pkt()
573 		data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);  in ti_hecc_rx_pkt()
576 	spin_lock_irqsave(&priv->mbx_lock, flags);  in ti_hecc_rx_pkt()
577 	hecc_clear_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_rx_pkt()
578 	hecc_write(priv, HECC_CANRMP, mbx_mask);  in ti_hecc_rx_pkt()
580 	if (priv->rx_next < HECC_RX_BUFFER_MBOX)  in ti_hecc_rx_pkt()
581 		hecc_set_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_rx_pkt()
582 	spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_rx_pkt()
585 	can_led_event(priv->ndev, CAN_LED_EVENT_RX);  in ti_hecc_rx_pkt()
616 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_rx_poll()  local
624 	while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&  in ti_hecc_rx_poll()
626 		mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */  in ti_hecc_rx_poll()
628 			if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)  in ti_hecc_rx_poll()
631 		} else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {  in ti_hecc_rx_poll()
634 		--priv->rx_next;  in ti_hecc_rx_poll()
635 		if (priv->rx_next == HECC_RX_BUFFER_MBOX) {  in ti_hecc_rx_poll()
637 			spin_lock_irqsave(&priv->mbx_lock, flags);  in ti_hecc_rx_poll()
638 			mbx_mask = hecc_read(priv, HECC_CANME);  in ti_hecc_rx_poll()
640 			hecc_write(priv, HECC_CANME, mbx_mask);  in ti_hecc_rx_poll()
641 			spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_rx_poll()
642 		} else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {  in ti_hecc_rx_poll()
643 			priv->rx_next = HECC_RX_FIRST_MBOX;  in ti_hecc_rx_poll()
649 	if (hecc_read(priv, HECC_CANRMP) == 0) {  in ti_hecc_rx_poll()
652 		mbx_mask = hecc_read(priv, HECC_CANMIM);  in ti_hecc_rx_poll()
654 		hecc_write(priv, HECC_CANMIM, mbx_mask);  in ti_hecc_rx_poll()
663 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_error()  local
672 			netdev_err(priv->ndev,  in ti_hecc_error()
679 			priv->can.state = CAN_STATE_ERROR_WARNING;  in ti_hecc_error()
680 			++priv->can.can_stats.error_warning;  in ti_hecc_error()
682 			if (hecc_read(priv, HECC_CANTEC) > 96)  in ti_hecc_error()
684 			if (hecc_read(priv, HECC_CANREC) > 96)  in ti_hecc_error()
687 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);  in ti_hecc_error()
688 		netdev_dbg(priv->ndev, "Error Warning interrupt\n");  in ti_hecc_error()
689 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);  in ti_hecc_error()
694 			priv->can.state = CAN_STATE_ERROR_PASSIVE;  in ti_hecc_error()
695 			++priv->can.can_stats.error_passive;  in ti_hecc_error()
697 			if (hecc_read(priv, HECC_CANTEC) > 127)  in ti_hecc_error()
699 			if (hecc_read(priv, HECC_CANREC) > 127)  in ti_hecc_error()
702 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);  in ti_hecc_error()
703 		netdev_dbg(priv->ndev, "Error passive interrupt\n");  in ti_hecc_error()
704 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);  in ti_hecc_error()
712 		priv->can.state = CAN_STATE_BUS_OFF;  in ti_hecc_error()
714 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);  in ti_hecc_error()
715 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);  in ti_hecc_error()
717 		hecc_write(priv, HECC_CANGIM, 0);  in ti_hecc_error()
718 		++priv->can.can_stats.bus_off;  in ti_hecc_error()
723 		++priv->can.can_stats.bus_error;  in ti_hecc_error()
726 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);  in ti_hecc_error()
730 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);  in ti_hecc_error()
734 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);  in ti_hecc_error()
738 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);  in ti_hecc_error()
742 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);  in ti_hecc_error()
757 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_interrupt()  local
762 	int_status = hecc_read(priv,  in ti_hecc_interrupt()
763 		(priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);  in ti_hecc_interrupt()
768 	err_status = hecc_read(priv, HECC_CANES);  in ti_hecc_interrupt()
774 		while (priv->tx_tail - priv->tx_head > 0) {  in ti_hecc_interrupt()
775 			mbxno = get_tx_tail_mb(priv);  in ti_hecc_interrupt()
777 			if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))  in ti_hecc_interrupt()
779 			hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);  in ti_hecc_interrupt()
780 			hecc_write(priv, HECC_CANTA, mbx_mask);  in ti_hecc_interrupt()
781 			spin_lock_irqsave(&priv->mbx_lock, flags);  in ti_hecc_interrupt()
782 			hecc_clear_bit(priv, HECC_CANME, mbx_mask);  in ti_hecc_interrupt()
783 			spin_unlock_irqrestore(&priv->mbx_lock, flags);  in ti_hecc_interrupt()
784 			stats->tx_bytes += hecc_read_mbx(priv, mbxno,  in ti_hecc_interrupt()
789 			--priv->tx_tail;  in ti_hecc_interrupt()
793 		if (((priv->tx_head == priv->tx_tail) &&  in ti_hecc_interrupt()
794 		((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||  in ti_hecc_interrupt()
795 		(((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&  in ti_hecc_interrupt()
796 		((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))  in ti_hecc_interrupt()
800 		if (hecc_read(priv, HECC_CANRMP)) {  in ti_hecc_interrupt()
801 			ack = hecc_read(priv, HECC_CANMIM);  in ti_hecc_interrupt()
803 			hecc_write(priv, HECC_CANMIM, ack);  in ti_hecc_interrupt()
804 			napi_schedule(&priv->napi);  in ti_hecc_interrupt()
809 	if (priv->int_line) {  in ti_hecc_interrupt()
810 		hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);  in ti_hecc_interrupt()
811 		int_status = hecc_read(priv, HECC_CANGIF1);  in ti_hecc_interrupt()
813 		hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);  in ti_hecc_interrupt()
814 		int_status = hecc_read(priv, HECC_CANGIF0);  in ti_hecc_interrupt()
822 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_open()  local
832 	ti_hecc_transceiver_switch(priv, 1);  in ti_hecc_open()
838 		ti_hecc_transceiver_switch(priv, 0);  in ti_hecc_open()
846 	napi_enable(&priv->napi);  in ti_hecc_open()
854 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_close()  local
857 	napi_disable(&priv->napi);  in ti_hecc_close()
861 	ti_hecc_transceiver_switch(priv, 0);  in ti_hecc_close()
878 	struct ti_hecc_priv *priv;  in ti_hecc_probe()  local
919 	priv = netdev_priv(ndev);  in ti_hecc_probe()
920 	priv->ndev = ndev;  in ti_hecc_probe()
921 	priv->base = addr;  in ti_hecc_probe()
922 	priv->scc_ram_offset = pdata->scc_ram_offset;  in ti_hecc_probe()
923 	priv->hecc_ram_offset = pdata->hecc_ram_offset;  in ti_hecc_probe()
924 	priv->mbx_offset = pdata->mbx_offset;  in ti_hecc_probe()
925 	priv->int_line = pdata->int_line;  in ti_hecc_probe()
926 	priv->transceiver_switch = pdata->transceiver_switch;  in ti_hecc_probe()
928 	priv->can.bittiming_const = &ti_hecc_bittiming_const;  in ti_hecc_probe()
929 	priv->can.do_set_mode = ti_hecc_do_set_mode;  in ti_hecc_probe()
930 	priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;  in ti_hecc_probe()
931 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;  in ti_hecc_probe()
933 	spin_lock_init(&priv->mbx_lock);  in ti_hecc_probe()
940 	priv->clk = clk_get(&pdev->dev, "hecc_ck");  in ti_hecc_probe()
941 	if (IS_ERR(priv->clk)) {  in ti_hecc_probe()
943 		err = PTR_ERR(priv->clk);  in ti_hecc_probe()
944 		priv->clk = NULL;  in ti_hecc_probe()
947 	priv->can.clock.freq = clk_get_rate(priv->clk);  in ti_hecc_probe()
948 	netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,  in ti_hecc_probe()
951 	clk_enable(priv->clk);  in ti_hecc_probe()
961 		priv->base, (u32) ndev->irq);  in ti_hecc_probe()
966 	clk_put(priv->clk);  in ti_hecc_probe()
981 	struct ti_hecc_priv *priv = netdev_priv(ndev);  in ti_hecc_remove()  local
984 	clk_disable(priv->clk);  in ti_hecc_remove()
985 	clk_put(priv->clk);  in ti_hecc_remove()
987 	iounmap(priv->base);  in ti_hecc_remove()
999 	struct ti_hecc_priv *priv = netdev_priv(dev);  in ti_hecc_suspend()  local
1006 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);  in ti_hecc_suspend()
1007 	priv->can.state = CAN_STATE_SLEEPING;  in ti_hecc_suspend()
1009 	clk_disable(priv->clk);  in ti_hecc_suspend()
1017 	struct ti_hecc_priv *priv = netdev_priv(dev);  in ti_hecc_resume()  local
1019 	clk_enable(priv->clk);  in ti_hecc_resume()
1021 	hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);  in ti_hecc_resume()
1022 	priv->can.state = CAN_STATE_ERROR_ACTIVE;  in ti_hecc_resume()