Lines Matching refs:priv
213 static void pch_can_set_run_mode(struct pch_can_priv *priv, in pch_can_set_run_mode() argument
218 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); in pch_can_set_run_mode()
222 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); in pch_can_set_run_mode()
226 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__); in pch_can_set_run_mode()
231 static void pch_can_set_optmode(struct pch_can_priv *priv) in pch_can_set_optmode() argument
233 u32 reg_val = ioread32(&priv->regs->opt); in pch_can_set_optmode()
235 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in pch_can_set_optmode()
238 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in pch_can_set_optmode()
241 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); in pch_can_set_optmode()
242 iowrite32(reg_val, &priv->regs->opt); in pch_can_set_optmode()
262 static void pch_can_set_int_enables(struct pch_can_priv *priv, in pch_can_set_int_enables() argument
267 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); in pch_can_set_int_enables()
271 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); in pch_can_set_int_enables()
275 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); in pch_can_set_int_enables()
279 netdev_err(priv->ndev, "Invalid interrupt number.\n"); in pch_can_set_int_enables()
284 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, in pch_can_set_rxtx() argument
295 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); in pch_can_set_rxtx()
296 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); in pch_can_set_rxtx()
300 &priv->regs->ifregs[dir].cmask); in pch_can_set_rxtx()
304 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); in pch_can_set_rxtx()
305 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); in pch_can_set_rxtx()
308 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); in pch_can_set_rxtx()
309 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); in pch_can_set_rxtx()
312 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); in pch_can_set_rxtx()
315 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set) in pch_can_set_rx_all() argument
321 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); in pch_can_set_rx_all()
324 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set) in pch_can_set_tx_all() argument
330 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); in pch_can_set_tx_all()
333 static u32 pch_can_int_pending(struct pch_can_priv *priv) in pch_can_int_pending() argument
335 return ioread32(&priv->regs->intr) & 0xffff; in pch_can_int_pending()
338 static void pch_can_clear_if_buffers(struct pch_can_priv *priv) in pch_can_clear_if_buffers() argument
343 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); in pch_can_clear_if_buffers()
344 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); in pch_can_clear_if_buffers()
345 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); in pch_can_clear_if_buffers()
346 iowrite32(0x0, &priv->regs->ifregs[0].id1); in pch_can_clear_if_buffers()
347 iowrite32(0x0, &priv->regs->ifregs[0].id2); in pch_can_clear_if_buffers()
348 iowrite32(0x0, &priv->regs->ifregs[0].mcont); in pch_can_clear_if_buffers()
349 iowrite32(0x0, &priv->regs->ifregs[0].data[0]); in pch_can_clear_if_buffers()
350 iowrite32(0x0, &priv->regs->ifregs[0].data[1]); in pch_can_clear_if_buffers()
351 iowrite32(0x0, &priv->regs->ifregs[0].data[2]); in pch_can_clear_if_buffers()
352 iowrite32(0x0, &priv->regs->ifregs[0].data[3]); in pch_can_clear_if_buffers()
355 &priv->regs->ifregs[0].cmask); in pch_can_clear_if_buffers()
356 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); in pch_can_clear_if_buffers()
360 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) in pch_can_config_rx_tx_buffers() argument
365 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); in pch_can_config_rx_tx_buffers()
366 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); in pch_can_config_rx_tx_buffers()
368 iowrite32(0x0, &priv->regs->ifregs[0].id1); in pch_can_config_rx_tx_buffers()
369 iowrite32(0x0, &priv->regs->ifregs[0].id2); in pch_can_config_rx_tx_buffers()
371 pch_can_bit_set(&priv->regs->ifregs[0].mcont, in pch_can_config_rx_tx_buffers()
376 pch_can_bit_set(&priv->regs->ifregs[0].mcont, in pch_can_config_rx_tx_buffers()
379 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, in pch_can_config_rx_tx_buffers()
382 iowrite32(0, &priv->regs->ifregs[0].mask1); in pch_can_config_rx_tx_buffers()
383 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, in pch_can_config_rx_tx_buffers()
388 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask); in pch_can_config_rx_tx_buffers()
390 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); in pch_can_config_rx_tx_buffers()
394 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); in pch_can_config_rx_tx_buffers()
395 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); in pch_can_config_rx_tx_buffers()
398 iowrite32(0x0, &priv->regs->ifregs[1].id1); in pch_can_config_rx_tx_buffers()
399 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2); in pch_can_config_rx_tx_buffers()
403 &priv->regs->ifregs[1].mcont); in pch_can_config_rx_tx_buffers()
405 iowrite32(0, &priv->regs->ifregs[1].mask1); in pch_can_config_rx_tx_buffers()
406 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); in pch_can_config_rx_tx_buffers()
410 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask); in pch_can_config_rx_tx_buffers()
412 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); in pch_can_config_rx_tx_buffers()
416 static void pch_can_init(struct pch_can_priv *priv) in pch_can_init() argument
419 pch_can_set_run_mode(priv, PCH_CAN_STOP); in pch_can_init()
422 pch_can_clear_if_buffers(priv); in pch_can_init()
425 pch_can_config_rx_tx_buffers(priv); in pch_can_init()
428 pch_can_set_int_enables(priv, PCH_CAN_ALL); in pch_can_init()
431 static void pch_can_release(struct pch_can_priv *priv) in pch_can_release() argument
434 pch_can_set_run_mode(priv, PCH_CAN_STOP); in pch_can_release()
437 pch_can_set_int_enables(priv, PCH_CAN_NONE); in pch_can_release()
440 pch_can_set_rx_all(priv, 0); in pch_can_release()
443 pch_can_set_tx_all(priv, 0); in pch_can_release()
447 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) in pch_can_int_clr() argument
453 &priv->regs->ifregs[0].cmask); in pch_can_int_clr()
456 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); in pch_can_int_clr()
459 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, in pch_can_int_clr()
462 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask); in pch_can_int_clr()
468 &priv->regs->ifregs[1].cmask); in pch_can_int_clr()
471 pch_can_bit_set(&priv->regs->ifregs[1].id2, in pch_can_int_clr()
473 iowrite32(0x0, &priv->regs->ifregs[1].id1); in pch_can_int_clr()
476 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, in pch_can_int_clr()
479 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask); in pch_can_int_clr()
483 static void pch_can_reset(struct pch_can_priv *priv) in pch_can_reset() argument
486 iowrite32(1, &priv->regs->srst); in pch_can_reset()
487 iowrite32(0, &priv->regs->srst); in pch_can_reset()
493 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_error() local
496 struct net_device_stats *stats = &(priv->ndev->stats); in pch_can_error()
497 enum can_state state = priv->can.state; in pch_can_error()
504 pch_can_set_tx_all(priv, 0); in pch_can_error()
505 pch_can_set_rx_all(priv, 0); in pch_can_error()
508 priv->can.can_stats.bus_off++; in pch_can_error()
512 errc = ioread32(&priv->regs->errc); in pch_can_error()
516 priv->can.can_stats.error_warning++; in pch_can_error()
527 priv->can.can_stats.error_passive++; in pch_can_error()
542 priv->can.can_stats.bus_error++; in pch_can_error()
547 priv->can.can_stats.bus_error++; in pch_can_error()
552 priv->can.can_stats.bus_error++; in pch_can_error()
558 priv->can.can_stats.bus_error++; in pch_can_error()
563 priv->can.can_stats.bus_error++; in pch_can_error()
573 priv->can.state = state; in pch_can_error()
583 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_interrupt() local
585 if (!pch_can_int_pending(priv)) in pch_can_interrupt()
588 pch_can_set_int_enables(priv, PCH_CAN_NONE); in pch_can_interrupt()
589 napi_schedule(&priv->napi); in pch_can_interrupt()
593 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id) in pch_fifo_thresh() argument
597 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); in pch_fifo_thresh()
600 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); in pch_fifo_thresh()
603 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, in pch_fifo_thresh()
605 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); in pch_fifo_thresh()
607 pch_can_int_clr(priv, obj_id); in pch_fifo_thresh()
611 pch_can_int_clr(priv, cnt + 1); in pch_fifo_thresh()
617 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_rx_msg_lost() local
618 struct net_device_stats *stats = &(priv->ndev->stats); in pch_can_rx_msg_lost()
622 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n"); in pch_can_rx_msg_lost()
623 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, in pch_can_rx_msg_lost()
626 &priv->regs->ifregs[0].cmask); in pch_can_rx_msg_lost()
627 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); in pch_can_rx_msg_lost()
648 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_rx_normal() local
649 struct net_device_stats *stats = &(priv->ndev->stats); in pch_can_rx_normal()
656 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); in pch_can_rx_normal()
657 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num); in pch_can_rx_normal()
660 reg = ioread32(&priv->regs->ifregs[0].mcont); in pch_can_rx_normal()
677 skb = alloc_can_skb(priv->ndev, &cf); in pch_can_rx_normal()
684 id2 = ioread32(&priv->regs->ifregs[0].id2); in pch_can_rx_normal()
686 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); in pch_can_rx_normal()
697 cf->can_dlc = get_can_dlc((ioread32(&priv->regs-> in pch_can_rx_normal()
701 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); in pch_can_rx_normal()
712 pch_fifo_thresh(priv, obj_num); in pch_can_rx_normal()
721 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_tx_complete() local
722 struct net_device_stats *stats = &(priv->ndev->stats); in pch_can_tx_complete()
727 &priv->regs->ifregs[1].cmask); in pch_can_tx_complete()
728 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat); in pch_can_tx_complete()
729 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & in pch_can_tx_complete()
740 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_poll() local
745 int_stat = pch_can_int_pending(priv); in pch_can_poll()
750 reg_stat = ioread32(&priv->regs->stat); in pch_can_poll()
759 pch_can_bit_clear(&priv->regs->stat, in pch_can_poll()
762 int_stat = pch_can_int_pending(priv); in pch_can_poll()
778 pch_can_set_int_enables(priv, PCH_CAN_ALL); in pch_can_poll()
785 struct pch_can_priv *priv = netdev_priv(ndev); in pch_set_bittiming() local
786 const struct can_bittiming *bt = &priv->can.bittiming; in pch_set_bittiming()
791 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); in pch_set_bittiming()
798 iowrite32(canbit, &priv->regs->bitt); in pch_set_bittiming()
799 iowrite32(bepe, &priv->regs->brpe); in pch_set_bittiming()
800 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); in pch_set_bittiming()
807 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_start() local
809 if (priv->can.state != CAN_STATE_STOPPED) in pch_can_start()
810 pch_can_reset(priv); in pch_can_start()
813 pch_can_set_optmode(priv); in pch_can_start()
815 pch_can_set_tx_all(priv, 1); in pch_can_start()
816 pch_can_set_rx_all(priv, 1); in pch_can_start()
819 pch_can_set_run_mode(priv, PCH_CAN_RUN); in pch_can_start()
821 priv->can.state = CAN_STATE_ERROR_ACTIVE; in pch_can_start()
845 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_open() local
849 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, in pch_can_open()
863 pch_can_init(priv); in pch_can_open()
865 napi_enable(&priv->napi); in pch_can_open()
871 free_irq(priv->dev->irq, ndev); in pch_can_open()
873 pch_can_release(priv); in pch_can_open()
880 struct pch_can_priv *priv = netdev_priv(ndev); in pch_close() local
883 napi_disable(&priv->napi); in pch_close()
884 pch_can_release(priv); in pch_close()
885 free_irq(priv->dev->irq, ndev); in pch_close()
887 priv->can.state = CAN_STATE_STOPPED; in pch_close()
893 struct pch_can_priv *priv = netdev_priv(ndev); in pch_xmit() local
902 tx_obj_no = priv->tx_obj; in pch_xmit()
903 if (priv->tx_obj == PCH_TX_OBJ_END) { in pch_xmit()
904 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) in pch_xmit()
907 priv->tx_obj = PCH_TX_OBJ_START; in pch_xmit()
909 priv->tx_obj++; in pch_xmit()
913 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); in pch_xmit()
917 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1); in pch_xmit()
920 iowrite32(0, &priv->regs->ifregs[1].id1); in pch_xmit()
930 iowrite32(id2, &priv->regs->ifregs[1].id2); in pch_xmit()
935 &priv->regs->ifregs[1].data[i / 2]); in pch_xmit()
942 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont); in pch_xmit()
944 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); in pch_xmit()
959 struct pch_can_priv *priv = netdev_priv(ndev); in pch_can_remove() local
961 unregister_candev(priv->ndev); in pch_can_remove()
962 if (priv->use_msi) in pch_can_remove()
963 pci_disable_msi(priv->dev); in pch_can_remove()
966 pch_can_reset(priv); in pch_can_remove()
967 pci_iounmap(pdev, priv->regs); in pch_can_remove()
968 free_candev(priv->ndev); in pch_can_remove()
972 static void pch_can_set_int_custom(struct pch_can_priv *priv) in pch_can_set_int_custom() argument
975 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); in pch_can_set_int_custom()
978 pch_can_bit_set(&priv->regs->cont, in pch_can_set_int_custom()
979 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); in pch_can_set_int_custom()
983 static u32 pch_can_get_int_enables(struct pch_can_priv *priv) in pch_can_get_int_enables() argument
986 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1; in pch_can_get_int_enables()
989 static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, in pch_can_get_rxtx_ir() argument
999 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); in pch_can_get_rxtx_ir()
1000 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); in pch_can_get_rxtx_ir()
1002 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && in pch_can_get_rxtx_ir()
1003 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) in pch_can_get_rxtx_ir()
1011 static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, in pch_can_set_rx_buffer_link() argument
1014 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); in pch_can_set_rx_buffer_link()
1015 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); in pch_can_set_rx_buffer_link()
1017 &priv->regs->ifregs[0].cmask); in pch_can_set_rx_buffer_link()
1019 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, in pch_can_set_rx_buffer_link()
1022 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); in pch_can_set_rx_buffer_link()
1024 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); in pch_can_set_rx_buffer_link()
1027 static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num) in pch_can_get_rx_buffer_link() argument
1031 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); in pch_can_get_rx_buffer_link()
1032 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); in pch_can_get_rx_buffer_link()
1034 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) in pch_can_get_rx_buffer_link()
1041 static int pch_can_get_buffer_status(struct pch_can_priv *priv) in pch_can_get_buffer_status() argument
1043 return (ioread32(&priv->regs->treq1) & 0xffff) | in pch_can_get_buffer_status()
1044 (ioread32(&priv->regs->treq2) << 16); in pch_can_get_buffer_status()
1055 struct pch_can_priv *priv = netdev_priv(dev); in pch_can_suspend() local
1058 pch_can_set_run_mode(priv, PCH_CAN_STOP); in pch_can_suspend()
1061 priv->can.state = CAN_STATE_STOPPED; in pch_can_suspend()
1065 buf_stat = pch_can_get_buffer_status(priv); in pch_can_suspend()
1075 priv->int_enables = pch_can_get_int_enables(priv); in pch_can_suspend()
1076 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); in pch_can_suspend()
1080 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, in pch_can_suspend()
1084 pch_can_set_tx_all(priv, 0); in pch_can_suspend()
1088 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, in pch_can_suspend()
1090 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i); in pch_can_suspend()
1094 pch_can_set_rx_all(priv, 0); in pch_can_suspend()
1112 struct pch_can_priv *priv = netdev_priv(dev); in pch_can_resume() local
1124 priv->can.state = CAN_STATE_ERROR_ACTIVE; in pch_can_resume()
1127 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); in pch_can_resume()
1130 pch_can_set_run_mode(priv, PCH_CAN_STOP); in pch_can_resume()
1133 pch_can_config_rx_tx_buffers(priv); in pch_can_resume()
1139 pch_can_set_optmode(priv); in pch_can_resume()
1143 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG); in pch_can_resume()
1148 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]); in pch_can_resume()
1151 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG); in pch_can_resume()
1155 pch_can_set_int_custom(priv); in pch_can_resume()
1158 pch_can_set_run_mode(priv, PCH_CAN_RUN); in pch_can_resume()
1170 struct pch_can_priv *priv = netdev_priv(dev); in pch_can_get_berr_counter() local
1171 u32 errc = ioread32(&priv->regs->errc); in pch_can_get_berr_counter()
1183 struct pch_can_priv *priv; in pch_can_probe() local
1213 priv = netdev_priv(ndev); in pch_can_probe()
1214 priv->ndev = ndev; in pch_can_probe()
1215 priv->regs = addr; in pch_can_probe()
1216 priv->dev = pdev; in pch_can_probe()
1217 priv->can.bittiming_const = &pch_can_bittiming_const; in pch_can_probe()
1218 priv->can.do_set_mode = pch_can_do_set_mode; in pch_can_probe()
1219 priv->can.do_get_berr_counter = pch_can_get_berr_counter; in pch_can_probe()
1220 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | in pch_can_probe()
1222 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ in pch_can_probe()
1230 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ in pch_can_probe()
1232 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END); in pch_can_probe()
1234 rc = pci_enable_msi(priv->dev); in pch_can_probe()
1237 priv->use_msi = 0; in pch_can_probe()
1241 priv->use_msi = 1; in pch_can_probe()
1253 if (priv->use_msi) in pch_can_probe()
1254 pci_disable_msi(priv->dev); in pch_can_probe()