302 static inline void flexcan_write(u32 val, void __iomem *addr)  in flexcan_write()  function
312 static inline void flexcan_write(u32 val, void __iomem *addr)  in flexcan_write()  function
349 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_enable()
368 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_disable()
387 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_freeze()
406 	flexcan_write(reg, &regs->mcr);  in flexcan_chip_unfreeze()
422 	flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);  in flexcan_chip_softreset()
494 		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);  in flexcan_start_xmit()
498 		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);  in flexcan_start_xmit()
503 	flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);  in flexcan_start_xmit()
504 	flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);  in flexcan_start_xmit()
509 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
511 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
650 	flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);  in flexcan_read_fifo()
708 		flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);  in flexcan_poll()
709 		flexcan_write(priv->reg_ctrl_default, &regs->ctrl);  in flexcan_poll()
728 		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);  in flexcan_irq()
742 		flexcan_write(FLEXCAN_IFLAG_DEFAULT &  in flexcan_irq()
744 		flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,  in flexcan_irq()
751 		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);  in flexcan_irq()
763 		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_irq()
765 		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);  in flexcan_irq()
803 	flexcan_write(reg, &regs->ctrl);  in flexcan_set_bittiming()
851 	flexcan_write(reg_mcr, &regs->mcr);  in flexcan_chip_start()
884 	flexcan_write(reg_ctrl, &regs->ctrl);  in flexcan_chip_start()
888 		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,  in flexcan_chip_start()
893 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
897 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
901 	flexcan_write(0x0, &regs->rxgmask);  in flexcan_chip_start()
902 	flexcan_write(0x0, &regs->rx14mask);  in flexcan_chip_start()
903 	flexcan_write(0x0, &regs->rx15mask);  in flexcan_chip_start()
906 		flexcan_write(0x0, &regs->rxfgmask);  in flexcan_chip_start()
921 		flexcan_write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
925 		flexcan_write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
928 		flexcan_write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
944 	flexcan_write(priv->reg_ctrl_default, &regs->ctrl);  in flexcan_chip_start()
945 	flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);  in flexcan_chip_start()
975 	flexcan_write(0, &regs->imask1);  in flexcan_chip_stop()
976 	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,  in flexcan_chip_stop()
1094 	flexcan_write(reg, &regs->ctrl);  in register_flexcandev()
1104 	flexcan_write(reg, &regs->mcr);  in register_flexcandev()