150 			cc770_write_reg(priv, msgobj[mo].config, msgcfg);  in enable_all_objs()
151 			cc770_write_reg(priv, msgobj[mo].ctrl0,  in enable_all_objs()
156 				cc770_write_reg(priv, msgobj[mo].ctrl1,  in enable_all_objs()
160 				cc770_write_reg(priv, msgobj[mo].ctrl1,  in enable_all_objs()
167 			cc770_write_reg(priv, msgobj[mo].ctrl1,  in enable_all_objs()
170 			cc770_write_reg(priv, msgobj[mo].ctrl0,  in enable_all_objs()
188 			cc770_write_reg(priv, msgobj[mo].ctrl1,  in disable_all_objs()
191 			cc770_write_reg(priv, msgobj[mo].ctrl0,  in disable_all_objs()
196 			cc770_write_reg(priv, msgobj[mo].ctrl1,  in disable_all_objs()
199 			cc770_write_reg(priv, msgobj[mo].ctrl0,  in disable_all_objs()
271 		cc770_write_reg(priv, msgobj[mo].ctrl0,  in chipset_init()
274 		cc770_write_reg(priv, msgobj[mo].ctrl0,  in chipset_init()
277 		cc770_write_reg(priv, msgobj[mo].ctrl1,  in chipset_init()
281 			cc770_write_reg(priv, msgobj[mo].data[data], 0);  in chipset_init()
283 			cc770_write_reg(priv, msgobj[mo].id[id], 0);  in chipset_init()
284 		cc770_write_reg(priv, msgobj[mo].config, 0);  in chipset_init()
317 	cc770_write_reg(priv, msgobj[1].data[1], 0x25);  in cc770_probe_chip()
318 	cc770_write_reg(priv, msgobj[2].data[3], 0x52);  in cc770_probe_chip()
319 	cc770_write_reg(priv, msgobj[10].data[6], 0xc3);  in cc770_probe_chip()
320 	if ((cc770_read_reg(priv, msgobj[1].data[1]) != 0x25) ||  in cc770_probe_chip()
321 	    (cc770_read_reg(priv, msgobj[2].data[3]) != 0x52) ||  in cc770_probe_chip()
322 	    (cc770_read_reg(priv, msgobj[10].data[6]) != 0xc3)) {  in cc770_probe_chip()
407 			    msgobj[mo].ctrl1) & TXRQST_UNC) == TXRQST_SET) {  in cc770_start_xmit()
420 	cc770_write_reg(priv, msgobj[mo].ctrl1,  in cc770_start_xmit()
422 	cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_start_xmit()
426 		cc770_write_reg(priv, msgobj[mo].config,  in cc770_start_xmit()
428 		cc770_write_reg(priv, msgobj[mo].id[3], id << 3);  in cc770_start_xmit()
429 		cc770_write_reg(priv, msgobj[mo].id[2], id >> 5);  in cc770_start_xmit()
430 		cc770_write_reg(priv, msgobj[mo].id[1], id >> 13);  in cc770_start_xmit()
431 		cc770_write_reg(priv, msgobj[mo].id[0], id >> 21);  in cc770_start_xmit()
434 		cc770_write_reg(priv, msgobj[mo].config, (dlc << 4) | rtr);  in cc770_start_xmit()
435 		cc770_write_reg(priv, msgobj[mo].id[0], id >> 3);  in cc770_start_xmit()
436 		cc770_write_reg(priv, msgobj[mo].id[1], id << 5);  in cc770_start_xmit()
440 		cc770_write_reg(priv, msgobj[mo].data[i], cf->data[i]);  in cc770_start_xmit()
445 	cc770_write_reg(priv, msgobj[mo].ctrl1,  in cc770_start_xmit()
456 	cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_start_xmit()
476 	config = cc770_read_reg(priv, msgobj[mo].config);  in cc770_rx()
490 			id = cc770_read_reg(priv, msgobj[mo].id[3]);  in cc770_rx()
491 			id |= cc770_read_reg(priv, msgobj[mo].id[2]) << 8;  in cc770_rx()
492 			id |= cc770_read_reg(priv, msgobj[mo].id[1]) << 16;  in cc770_rx()
493 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 24;  in cc770_rx()
497 			id = cc770_read_reg(priv, msgobj[mo].id[1]);  in cc770_rx()
498 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 8;  in cc770_rx()
505 			cf->data[i] = cc770_read_reg(priv, msgobj[mo].data[i]);  in cc770_rx()
622 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);  in cc770_rx_interrupt()
627 				if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) &  in cc770_rx_interrupt()
640 			cc770_write_reg(priv, msgobj[mo].ctrl1,  in cc770_rx_interrupt()
645 		cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_rx_interrupt()
648 		cc770_write_reg(priv, msgobj[mo].ctrl1,  in cc770_rx_interrupt()
662 		ctrl0 = cc770_read_reg(priv, msgobj[mo].ctrl0);  in cc770_rtr_interrupt()
666 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);  in cc770_rtr_interrupt()
669 		cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_rtr_interrupt()
672 		cc770_write_reg(priv, msgobj[mo].ctrl1,  in cc770_rtr_interrupt()
685 	cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_tx_interrupt()
691 	cc770_write_reg(priv, msgobj[mo].ctrl0,  in cc770_tx_interrupt()