216 	cc770_read_reg(priv, interrupt);  in set_reset_mode()
230 	cc770_read_reg(priv, interrupt);  in set_normal_mode()
264 	cc770_read_reg(priv, interrupt);  in chipset_init()
310 	if (cc770_read_reg(priv, cpu_interface) & CPUIF_RST) {  in cc770_probe_chip()
320 	if ((cc770_read_reg(priv, msgobj[1].data[1]) != 0x25) ||  in cc770_probe_chip()
321 	    (cc770_read_reg(priv, msgobj[2].data[3]) != 0x52) ||  in cc770_probe_chip()
322 	    (cc770_read_reg(priv, msgobj[10].data[6]) != 0xc3)) {  in cc770_probe_chip()
329 	if (cc770_read_reg(priv, control) & CTRL_EAF)  in cc770_probe_chip()
387 	bec->txerr = cc770_read_reg(priv, tx_error_counter);  in cc770_get_berr_counter()
388 	bec->rxerr = cc770_read_reg(priv, rx_error_counter);  in cc770_get_berr_counter()
406 	if ((cc770_read_reg(priv,  in cc770_start_xmit()
476 	config = cc770_read_reg(priv, msgobj[mo].config);  in cc770_rx()
490 			id = cc770_read_reg(priv, msgobj[mo].id[3]);  in cc770_rx()
491 			id |= cc770_read_reg(priv, msgobj[mo].id[2]) << 8;  in cc770_rx()
492 			id |= cc770_read_reg(priv, msgobj[mo].id[1]) << 16;  in cc770_rx()
493 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 24;  in cc770_rx()
497 			id = cc770_read_reg(priv, msgobj[mo].id[1]);  in cc770_rx()
498 			id |= cc770_read_reg(priv, msgobj[mo].id[0]) << 8;  in cc770_rx()
505 			cf->data[i] = cc770_read_reg(priv, msgobj[mo].data[i]);  in cc770_rx()
529 		cf->data[6] = cc770_read_reg(priv, tx_error_counter);  in cc770_err()
530 		cf->data[7] = cc770_read_reg(priv, rx_error_counter);  in cc770_err()
600 	status = cc770_read_reg(priv, status);  in cc770_status_interrupt()
622 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);  in cc770_rx_interrupt()
627 				if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) &  in cc770_rx_interrupt()
662 		ctrl0 = cc770_read_reg(priv, msgobj[mo].ctrl0);  in cc770_rtr_interrupt()
666 		ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1);  in cc770_rtr_interrupt()
715 		intid = cc770_read_reg(priv, interrupt);  in cc770_interrupt()