Lines Matching refs:LUT0
185 #define LUT0(ins, pad, opr) \ macro
189 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), in fsl_qspi_init_lut()
374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
390 writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); in fsl_qspi_init_lut()
394 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1), in fsl_qspi_init_lut()
403 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
408 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), in fsl_qspi_init_lut()
413 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8), in fsl_qspi_init_lut()
418 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2), in fsl_qspi_init_lut()
423 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1), in fsl_qspi_init_lut()
428 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
432 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
436 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()