110 	struct s3c2410_nand_info	*info;  member
176 	return s3c2410_nand_mtd_toours(mtd)->info;  in s3c2410_nand_mtd_toinfo()
189 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)  in allow_clk_suspend()  argument
203 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,  in s3c2410_nand_clk_set_state()  argument
206 	if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)  in s3c2410_nand_clk_set_state()
209 	if (info->clk_state == CLOCK_ENABLE) {  in s3c2410_nand_clk_set_state()
211 			clk_disable_unprepare(info->clk);  in s3c2410_nand_clk_set_state()
214 			clk_prepare_enable(info->clk);  in s3c2410_nand_clk_set_state()
217 	info->clk_state = new_state;  in s3c2410_nand_clk_set_state()
264 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)  in s3c2410_nand_setrate()  argument
266 	struct s3c2410_platform_nand *plat = info->platform;  in s3c2410_nand_setrate()
267 	int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;  in s3c2410_nand_setrate()
269 	unsigned long clkrate = clk_get_rate(info->clk);  in s3c2410_nand_setrate()
275 	info->clk_rate = clkrate;  in s3c2410_nand_setrate()
290 		dev_err(info->device, "cannot get suitable timings\n");  in s3c2410_nand_setrate()
294 	dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",  in s3c2410_nand_setrate()
298 	switch (info->cpu_type) {  in s3c2410_nand_setrate()
326 	cfg = readl(info->regs + S3C2410_NFCONF);  in s3c2410_nand_setrate()
329 	writel(cfg, info->regs + S3C2410_NFCONF);  in s3c2410_nand_setrate()
333 	dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);  in s3c2410_nand_setrate()
345 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)  in s3c2410_nand_inithw()  argument
349 	ret = s3c2410_nand_setrate(info);  in s3c2410_nand_inithw()
353 	switch (info->cpu_type) {  in s3c2410_nand_inithw()
362 		writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);  in s3c2410_nand_inithw()
383 	struct s3c2410_nand_info *info;  in s3c2410_nand_select_chip()  local
389 	info = nmtd->info;  in s3c2410_nand_select_chip()
392 		s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);  in s3c2410_nand_select_chip()
394 	cur = readl(info->sel_reg);  in s3c2410_nand_select_chip()
397 		cur |= info->sel_bit;  in s3c2410_nand_select_chip()
400 			dev_err(info->device, "invalid chip %d\n", chip);  in s3c2410_nand_select_chip()
404 		if (info->platform != NULL) {  in s3c2410_nand_select_chip()
405 			if (info->platform->select_chip != NULL)  in s3c2410_nand_select_chip()
406 				(info->platform->select_chip) (nmtd->set, chip);  in s3c2410_nand_select_chip()
409 		cur &= ~info->sel_bit;  in s3c2410_nand_select_chip()
412 	writel(cur, info->sel_reg);  in s3c2410_nand_select_chip()
415 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);  in s3c2410_nand_select_chip()
426 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2410_nand_hwcontrol()  local
432 		writeb(cmd, info->regs + S3C2410_NFCMD);  in s3c2410_nand_hwcontrol()
434 		writeb(cmd, info->regs + S3C2410_NFADDR);  in s3c2410_nand_hwcontrol()
442 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_hwcontrol()  local
448 		writeb(cmd, info->regs + S3C2440_NFCMD);  in s3c2440_nand_hwcontrol()
450 		writeb(cmd, info->regs + S3C2440_NFADDR);  in s3c2440_nand_hwcontrol()
460 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2410_nand_devready()  local
461 	return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;  in s3c2410_nand_devready()
466 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_devready()  local
467 	return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;  in s3c2440_nand_devready()
472 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2412_nand_devready()  local
473 	return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;  in s3c2412_nand_devready()
482 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2410_nand_correct_data()  local
504 	    && info->platform->ignore_unset_ecc)  in s3c2410_nand_correct_data()
531 		dev_dbg(info->device, "correcting error bit %d, byte %d\n",  in s3c2410_nand_correct_data()
559 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2410_nand_enable_hwecc()  local
562 	ctrl = readl(info->regs + S3C2410_NFCONF);  in s3c2410_nand_enable_hwecc()
564 	writel(ctrl, info->regs + S3C2410_NFCONF);  in s3c2410_nand_enable_hwecc()
569 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2412_nand_enable_hwecc()  local
572 	ctrl = readl(info->regs + S3C2440_NFCONT);  in s3c2412_nand_enable_hwecc()
574 	       info->regs + S3C2440_NFCONT);  in s3c2412_nand_enable_hwecc()
579 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_enable_hwecc()  local
582 	ctrl = readl(info->regs + S3C2440_NFCONT);  in s3c2440_nand_enable_hwecc()
583 	writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);  in s3c2440_nand_enable_hwecc()
589 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2410_nand_calculate_ecc()  local
591 	ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);  in s3c2410_nand_calculate_ecc()
592 	ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);  in s3c2410_nand_calculate_ecc()
593 	ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);  in s3c2410_nand_calculate_ecc()
603 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2412_nand_calculate_ecc()  local
604 	unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);  in s3c2412_nand_calculate_ecc()
618 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_calculate_ecc()  local
619 	unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);  in s3c2440_nand_calculate_ecc()
643 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_read_buf()  local
645 	readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);  in s3c2440_nand_read_buf()
652 			*buf++ = readb(info->regs + S3C2440_NFDATA);  in s3c2440_nand_read_buf()
666 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);  in s3c2440_nand_write_buf()  local
668 	writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);  in s3c2440_nand_write_buf()
675 			writeb(*buf, info->regs + S3C2440_NFDATA);  in s3c2440_nand_write_buf()
686 	struct s3c2410_nand_info *info;  in s3c2410_nand_cpufreq_transition()  local
689 	info = container_of(nb, struct s3c2410_nand_info, freq_transition);  in s3c2410_nand_cpufreq_transition()
690 	newclk = clk_get_rate(info->clk);  in s3c2410_nand_cpufreq_transition()
692 	if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||  in s3c2410_nand_cpufreq_transition()
693 	    (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {  in s3c2410_nand_cpufreq_transition()
694 		s3c2410_nand_setrate(info);  in s3c2410_nand_cpufreq_transition()
700 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)  in s3c2410_nand_cpufreq_register()  argument
702 	info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;  in s3c2410_nand_cpufreq_register()
704 	return cpufreq_register_notifier(&info->freq_transition,  in s3c2410_nand_cpufreq_register()
709 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)  in s3c2410_nand_cpufreq_deregister()  argument
711 	cpufreq_unregister_notifier(&info->freq_transition,  in s3c2410_nand_cpufreq_deregister()
716 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)  in s3c2410_nand_cpufreq_register()  argument
722 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)  in s3c2410_nand_cpufreq_deregister()  argument
731 	struct s3c2410_nand_info *info = to_nand_info(pdev);  in s3c24xx_nand_remove()  local
733 	if (info == NULL)  in s3c24xx_nand_remove()
736 	s3c2410_nand_cpufreq_deregister(info);  in s3c24xx_nand_remove()
742 	if (info->mtds != NULL) {  in s3c24xx_nand_remove()
743 		struct s3c2410_nand_mtd *ptr = info->mtds;  in s3c24xx_nand_remove()
746 		for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {  in s3c24xx_nand_remove()
754 	if (!IS_ERR(info->clk))  in s3c24xx_nand_remove()
755 		s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);  in s3c24xx_nand_remove()
760 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,  in s3c2410_nand_add_partition()  argument
784 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,  in s3c2410_nand_init_chip()  argument
789 	void __iomem *regs = info->regs;  in s3c2410_nand_init_chip()
797 	chip->controller   = &info->controller;  in s3c2410_nand_init_chip()
799 	switch (info->cpu_type) {  in s3c2410_nand_init_chip()
802 		info->sel_reg   = regs + S3C2410_NFCONF;  in s3c2410_nand_init_chip()
803 		info->sel_bit	= S3C2410_NFCONF_nFCE;  in s3c2410_nand_init_chip()
810 		info->sel_reg   = regs + S3C2440_NFCONT;  in s3c2410_nand_init_chip()
811 		info->sel_bit	= S3C2440_NFCONT_nFCE;  in s3c2410_nand_init_chip()
820 		info->sel_reg   = regs + S3C2440_NFCONT;  in s3c2410_nand_init_chip()
821 		info->sel_bit	= S3C2412_NFCONT_nFCE0;  in s3c2410_nand_init_chip()
826 			dev_info(info->device, "System booted from NAND\n");  in s3c2410_nand_init_chip()
833 	nmtd->info	   = info;  in s3c2410_nand_init_chip()
843 	switch (info->cpu_type) {  in s3c2410_nand_init_chip()
871 		dev_info(info->device, "NAND ECC disabled\n");  in s3c2410_nand_init_chip()
874 		dev_info(info->device, "NAND soft ECC\n");  in s3c2410_nand_init_chip()
877 		dev_info(info->device, "NAND hardware ECC\n");  in s3c2410_nand_init_chip()
880 		dev_info(info->device, "NAND ECC UNKNOWN\n");  in s3c2410_nand_init_chip()
904 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,  in s3c2410_nand_update_chip()  argument
909 	dev_dbg(info->device, "chip %p => page shift %d\n",  in s3c2410_nand_update_chip()
939 	struct s3c2410_nand_info *info;  in s3c24xx_nand_probe()  local
950 	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);  in s3c24xx_nand_probe()
951 	if (info == NULL) {  in s3c24xx_nand_probe()
956 	platform_set_drvdata(pdev, info);  in s3c24xx_nand_probe()
958 	spin_lock_init(&info->controller.lock);  in s3c24xx_nand_probe()
959 	init_waitqueue_head(&info->controller.wq);  in s3c24xx_nand_probe()
963 	info->clk = devm_clk_get(&pdev->dev, "nand");  in s3c24xx_nand_probe()
964 	if (IS_ERR(info->clk)) {  in s3c24xx_nand_probe()
970 	s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);  in s3c24xx_nand_probe()
978 	info->device	= &pdev->dev;  in s3c24xx_nand_probe()
979 	info->platform	= plat;  in s3c24xx_nand_probe()
980 	info->cpu_type	= cpu_type;  in s3c24xx_nand_probe()
982 	info->regs = devm_ioremap_resource(&pdev->dev, res);  in s3c24xx_nand_probe()
983 	if (IS_ERR(info->regs)) {  in s3c24xx_nand_probe()
984 		err = PTR_ERR(info->regs);  in s3c24xx_nand_probe()
988 	dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);  in s3c24xx_nand_probe()
992 	err = s3c2410_nand_inithw(info);  in s3c24xx_nand_probe()
999 	info->mtd_count = nr_sets;  in s3c24xx_nand_probe()
1003 	size = nr_sets * sizeof(*info->mtds);  in s3c24xx_nand_probe()
1004 	info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);  in s3c24xx_nand_probe()
1005 	if (info->mtds == NULL) {  in s3c24xx_nand_probe()
1012 	nmtd = info->mtds;  in s3c24xx_nand_probe()
1016 			 setno, nmtd, info);  in s3c24xx_nand_probe()
1019 		s3c2410_nand_init_chip(info, nmtd, sets);  in s3c24xx_nand_probe()
1026 			s3c2410_nand_update_chip(info, nmtd);  in s3c24xx_nand_probe()
1028 			s3c2410_nand_add_partition(info, nmtd, sets);  in s3c24xx_nand_probe()
1035 	err = s3c2410_nand_cpufreq_register(info);  in s3c24xx_nand_probe()
1041 	if (allow_clk_suspend(info)) {  in s3c24xx_nand_probe()
1043 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);  in s3c24xx_nand_probe()
1061 	struct s3c2410_nand_info *info = platform_get_drvdata(dev);  in s3c24xx_nand_suspend()  local
1063 	if (info) {  in s3c24xx_nand_suspend()
1064 		info->save_sel = readl(info->sel_reg);  in s3c24xx_nand_suspend()
1071 		writel(info->save_sel | info->sel_bit, info->sel_reg);  in s3c24xx_nand_suspend()
1073 		s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);  in s3c24xx_nand_suspend()
1081 	struct s3c2410_nand_info *info = platform_get_drvdata(dev);  in s3c24xx_nand_resume()  local
1084 	if (info) {  in s3c24xx_nand_resume()
1085 		s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);  in s3c24xx_nand_resume()
1086 		s3c2410_nand_inithw(info);  in s3c24xx_nand_resume()
1090 		sel = readl(info->sel_reg);  in s3c24xx_nand_resume()
1091 		sel &= ~info->sel_bit;  in s3c24xx_nand_resume()
1092 		sel |= info->save_sel & info->sel_bit;  in s3c24xx_nand_resume()
1093 		writel(sel, info->sel_reg);  in s3c24xx_nand_resume()
1095 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);  in s3c24xx_nand_resume()