139 #define nand_writel(info, off, val)	\  macro
408 	nand_writel(info, NDTR0CS0, ndtr0);  in pxa3xx_nand_set_timing()
409 	nand_writel(info, NDTR1CS0, ndtr1);  in pxa3xx_nand_set_timing()
447 	nand_writel(info, NDTR0CS0, ndtr0);  in pxa3xx_nand_set_sdr_timing()
448 	nand_writel(info, NDTR1CS0, ndtr1);  in pxa3xx_nand_set_sdr_timing()
568 			nand_writel(info, NDECCCTRL, 0x1);  in pxa3xx_nand_start()
572 			nand_writel(info, NDECCCTRL, 0x0);  in pxa3xx_nand_start()
588 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_start()
589 	nand_writel(info, NDCR, 0);  in pxa3xx_nand_start()
590 	nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_start()
607 		nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_stop()
613 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_stop()
622 	nand_writel(info, NDCR, ndcr & ~int_mask);  in enable_int()
630 	nand_writel(info, NDCR, ndcr | int_mask);  in disable_int()
718 	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);  in pxa3xx_nand_data_dma_irq()
766 	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);  in pxa3xx_nand_irq_thread()
836 	nand_writel(info, NDSR, status);  in pxa3xx_nand_irq()
850 		nand_writel(info, NDCB0, info->ndcb0);  in pxa3xx_nand_irq()
851 		nand_writel(info, NDCB0, info->ndcb1);  in pxa3xx_nand_irq()
852 		nand_writel(info, NDCB0, info->ndcb2);  in pxa3xx_nand_irq()
856 			nand_writel(info, NDCB0, info->ndcb3);  in pxa3xx_nand_irq()
1140 		nand_writel(info, NDTR0CS0, info->ndtr0cs0);  in nand_cmdfunc()
1141 		nand_writel(info, NDTR1CS0, info->ndtr1cs0);  in nand_cmdfunc()
1188 		nand_writel(info, NDTR0CS0, info->ndtr0cs0);  in nand_cmdfunc_extended()
1189 		nand_writel(info, NDTR1CS0, info->ndtr1cs0);  in nand_cmdfunc_extended()
1616 		nand_writel(info, NDECCCTRL, 0x0);  in pxa3xx_nand_scan()
1842 	nand_writel(info, NDCR,  in pxa3xx_nand_remove()
1985 	nand_writel(info, NDSR, NDSR_MASK);  in pxa3xx_nand_resume()