Lines Matching refs:info
139 #define nand_writel(info, off, val) \ argument
140 writel_relaxed((val), (info)->mmio_base + (off))
142 #define nand_readl(info, off) \ argument
143 readl_relaxed((info)->mmio_base + (off))
391 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_timing() local
392 unsigned long nand_clk = clk_get_rate(info->clk); in pxa3xx_nand_set_timing()
406 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_timing()
407 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_timing()
408 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_timing()
409 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_timing()
415 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_sdr_timing() local
417 unsigned long nand_clk = clk_get_rate(info->clk); in pxa3xx_nand_set_sdr_timing()
445 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_sdr_timing()
446 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_sdr_timing()
447 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_sdr_timing()
448 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_sdr_timing()
456 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_init_timings_compat() local
475 dev_err(&info->pdev->dev, "Error: timings not found\n"); in pxa3xx_nand_init_timings_compat()
508 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_init() local
520 info->reg_ndcr |= NDCR_DWIDTH_M; in pxa3xx_nand_init()
524 info->reg_ndcr |= (dfc_width == 16) ? NDCR_DWIDTH_C : 0; in pxa3xx_nand_init()
539 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info, in pxa3xx_set_datasize() argument
542 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; in pxa3xx_set_datasize()
544 info->data_size = mtd->writesize; in pxa3xx_set_datasize()
548 info->oob_size = info->spare_size; in pxa3xx_set_datasize()
549 if (!info->use_ecc) in pxa3xx_set_datasize()
550 info->oob_size += info->ecc_size; in pxa3xx_set_datasize()
559 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) in pxa3xx_nand_start() argument
563 ndcr = info->reg_ndcr; in pxa3xx_nand_start()
565 if (info->use_ecc) { in pxa3xx_nand_start()
567 if (info->ecc_bch) in pxa3xx_nand_start()
568 nand_writel(info, NDECCCTRL, 0x1); in pxa3xx_nand_start()
571 if (info->ecc_bch) in pxa3xx_nand_start()
572 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_start()
575 if (info->use_dma) in pxa3xx_nand_start()
580 if (info->use_spare) in pxa3xx_nand_start()
588 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_start()
589 nand_writel(info, NDCR, 0); in pxa3xx_nand_start()
590 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_start()
593 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) in pxa3xx_nand_stop() argument
599 ndcr = nand_readl(info, NDCR); in pxa3xx_nand_stop()
601 ndcr = nand_readl(info, NDCR); in pxa3xx_nand_stop()
607 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_stop()
609 if (info->dma_chan) in pxa3xx_nand_stop()
610 dmaengine_terminate_all(info->dma_chan); in pxa3xx_nand_stop()
613 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_stop()
617 enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in enable_int() argument
621 ndcr = nand_readl(info, NDCR); in enable_int()
622 nand_writel(info, NDCR, ndcr & ~int_mask); in enable_int()
625 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in disable_int() argument
629 ndcr = nand_readl(info, NDCR); in disable_int()
630 nand_writel(info, NDCR, ndcr | int_mask); in disable_int()
633 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) in drain_fifo() argument
635 if (info->ecc_bch) { in drain_fifo()
648 ioread32_rep(info->mmio_base + NDDB, data, 8); in drain_fifo()
650 ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val, in drain_fifo()
653 dev_err(&info->pdev->dev, in drain_fifo()
663 ioread32_rep(info->mmio_base + NDDB, data, len); in drain_fifo()
666 static void handle_data_pio(struct pxa3xx_nand_info *info) in handle_data_pio() argument
668 unsigned int do_bytes = min(info->data_size, info->chunk_size); in handle_data_pio()
670 switch (info->state) { in handle_data_pio()
672 writesl(info->mmio_base + NDDB, in handle_data_pio()
673 info->data_buff + info->data_buff_pos, in handle_data_pio()
676 if (info->oob_size > 0) in handle_data_pio()
677 writesl(info->mmio_base + NDDB, in handle_data_pio()
678 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
679 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
682 drain_fifo(info, in handle_data_pio()
683 info->data_buff + info->data_buff_pos, in handle_data_pio()
686 if (info->oob_size > 0) in handle_data_pio()
687 drain_fifo(info, in handle_data_pio()
688 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
689 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
692 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in handle_data_pio()
693 info->state); in handle_data_pio()
698 info->data_buff_pos += do_bytes; in handle_data_pio()
699 info->oob_buff_pos += info->oob_size; in handle_data_pio()
700 info->data_size -= do_bytes; in handle_data_pio()
705 struct pxa3xx_nand_info *info = data; in pxa3xx_nand_data_dma_irq() local
709 status = dmaengine_tx_status(info->dma_chan, info->dma_cookie, &state); in pxa3xx_nand_data_dma_irq()
711 info->state = STATE_DMA_DONE; in pxa3xx_nand_data_dma_irq()
713 dev_err(&info->pdev->dev, "DMA error on data channel\n"); in pxa3xx_nand_data_dma_irq()
714 info->retcode = ERR_DMABUSERR; in pxa3xx_nand_data_dma_irq()
716 dma_unmap_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir); in pxa3xx_nand_data_dma_irq()
718 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_data_dma_irq()
719 enable_int(info, NDCR_INT_MASK); in pxa3xx_nand_data_dma_irq()
722 static void start_data_dma(struct pxa3xx_nand_info *info) in start_data_dma() argument
727 switch (info->state) { in start_data_dma()
729 info->dma_dir = DMA_TO_DEVICE; in start_data_dma()
733 info->dma_dir = DMA_FROM_DEVICE; in start_data_dma()
737 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in start_data_dma()
738 info->state); in start_data_dma()
741 info->sg.length = info->data_size + in start_data_dma()
742 (info->oob_size ? info->spare_size + info->ecc_size : 0); in start_data_dma()
743 dma_map_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir); in start_data_dma()
745 tx = dmaengine_prep_slave_sg(info->dma_chan, &info->sg, 1, direction, in start_data_dma()
748 dev_err(&info->pdev->dev, "prep_slave_sg() failed\n"); in start_data_dma()
752 tx->callback_param = info; in start_data_dma()
753 info->dma_cookie = dmaengine_submit(tx); in start_data_dma()
754 dma_async_issue_pending(info->dma_chan); in start_data_dma()
755 dev_dbg(&info->pdev->dev, "%s(dir=%d cookie=%x size=%u)\n", in start_data_dma()
756 __func__, direction, info->dma_cookie, info->sg.length); in start_data_dma()
761 struct pxa3xx_nand_info *info = data; in pxa3xx_nand_irq_thread() local
763 handle_data_pio(info); in pxa3xx_nand_irq_thread()
765 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq_thread()
766 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_irq_thread()
773 struct pxa3xx_nand_info *info = devid; in pxa3xx_nand_irq() local
778 if (info->cs == 0) { in pxa3xx_nand_irq()
786 status = nand_readl(info, NDSR); in pxa3xx_nand_irq()
789 info->retcode = ERR_UNCORERR; in pxa3xx_nand_irq()
791 info->retcode = ERR_CORERR; in pxa3xx_nand_irq()
792 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && in pxa3xx_nand_irq()
793 info->ecc_bch) in pxa3xx_nand_irq()
794 info->ecc_err_cnt = NDSR_ERR_CNT(status); in pxa3xx_nand_irq()
796 info->ecc_err_cnt = 1; in pxa3xx_nand_irq()
803 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_irq()
804 info->max_bitflips, in pxa3xx_nand_irq()
805 info->ecc_err_cnt); in pxa3xx_nand_irq()
809 if (info->use_dma) { in pxa3xx_nand_irq()
810 disable_int(info, NDCR_INT_MASK); in pxa3xx_nand_irq()
811 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
813 start_data_dma(info); in pxa3xx_nand_irq()
816 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
823 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq()
827 info->state = STATE_READY; in pxa3xx_nand_irq()
836 nand_writel(info, NDSR, status); in pxa3xx_nand_irq()
840 info->state = STATE_CMD_HANDLE; in pxa3xx_nand_irq()
850 nand_writel(info, NDCB0, info->ndcb0); in pxa3xx_nand_irq()
851 nand_writel(info, NDCB0, info->ndcb1); in pxa3xx_nand_irq()
852 nand_writel(info, NDCB0, info->ndcb2); in pxa3xx_nand_irq()
855 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_irq()
856 nand_writel(info, NDCB0, info->ndcb3); in pxa3xx_nand_irq()
860 complete(&info->cmd_complete); in pxa3xx_nand_irq()
862 complete(&info->dev_ready); in pxa3xx_nand_irq()
875 static void set_command_address(struct pxa3xx_nand_info *info, in set_command_address() argument
880 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) in set_command_address()
883 info->ndcb2 = 0; in set_command_address()
885 info->ndcb1 = ((page_addr & 0xFFFF) << 16) in set_command_address()
889 info->ndcb2 = (page_addr & 0xFF0000) >> 16; in set_command_address()
891 info->ndcb2 = 0; in set_command_address()
895 static void prepare_start_command(struct pxa3xx_nand_info *info, int command) in prepare_start_command() argument
897 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
901 info->buf_start = 0; in prepare_start_command()
902 info->buf_count = 0; in prepare_start_command()
903 info->oob_size = 0; in prepare_start_command()
904 info->data_buff_pos = 0; in prepare_start_command()
905 info->oob_buff_pos = 0; in prepare_start_command()
906 info->use_ecc = 0; in prepare_start_command()
907 info->use_spare = 1; in prepare_start_command()
908 info->retcode = ERR_NONE; in prepare_start_command()
909 info->ecc_err_cnt = 0; in prepare_start_command()
910 info->ndcb3 = 0; in prepare_start_command()
911 info->need_wait = 0; in prepare_start_command()
916 info->use_ecc = 1; in prepare_start_command()
918 pxa3xx_set_datasize(info, mtd); in prepare_start_command()
921 info->use_spare = 0; in prepare_start_command()
924 info->ndcb1 = 0; in prepare_start_command()
925 info->ndcb2 = 0; in prepare_start_command()
937 info->buf_count = mtd->writesize + mtd->oobsize; in prepare_start_command()
938 memset(info->data_buff, 0xFF, info->buf_count); in prepare_start_command()
943 static int prepare_set_command(struct pxa3xx_nand_info *info, int command, in prepare_set_command() argument
950 host = info->host[info->cs]; in prepare_set_command()
955 if (info->cs != 0) in prepare_set_command()
956 info->ndcb0 = NDCB0_CSEL; in prepare_set_command()
958 info->ndcb0 = 0; in prepare_set_command()
969 info->buf_start = column; in prepare_set_command()
970 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
975 info->buf_start += mtd->writesize; in prepare_set_command()
983 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); in prepare_set_command()
985 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) in prepare_set_command()
988 info->ndcb3 = info->chunk_size + in prepare_set_command()
989 info->oob_size; in prepare_set_command()
992 set_command_address(info, mtd->writesize, column, page_addr); in prepare_set_command()
997 info->buf_start = column; in prepare_set_command()
998 set_command_address(info, mtd->writesize, 0, page_addr); in prepare_set_command()
1005 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
1010 info->data_size = 0; in prepare_set_command()
1016 if (is_buf_blank(info->data_buff, in prepare_set_command()
1029 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
1032 info->ndcb3 = info->chunk_size + in prepare_set_command()
1033 info->oob_size; in prepare_set_command()
1039 if (info->data_size == 0) { in prepare_set_command()
1040 info->ndcb0 = NDCB0_CMD_TYPE(0x1) in prepare_set_command()
1043 info->ndcb1 = 0; in prepare_set_command()
1044 info->ndcb2 = 0; in prepare_set_command()
1045 info->ndcb3 = 0; in prepare_set_command()
1048 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
1059 info->buf_count = INIT_BUFFER_SIZE; in prepare_set_command()
1060 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
1064 info->ndcb1 = (column & 0xFF); in prepare_set_command()
1065 info->ndcb3 = INIT_BUFFER_SIZE; in prepare_set_command()
1066 info->data_size = INIT_BUFFER_SIZE; in prepare_set_command()
1070 info->buf_count = READ_ID_BYTES; in prepare_set_command()
1071 info->ndcb0 |= NDCB0_CMD_TYPE(3) in prepare_set_command()
1074 info->ndcb1 = (column & 0xFF); in prepare_set_command()
1076 info->data_size = 8; in prepare_set_command()
1079 info->buf_count = 1; in prepare_set_command()
1080 info->ndcb0 |= NDCB0_CMD_TYPE(4) in prepare_set_command()
1084 info->data_size = 8; in prepare_set_command()
1088 info->ndcb0 |= NDCB0_CMD_TYPE(2) in prepare_set_command()
1094 info->ndcb1 = page_addr; in prepare_set_command()
1095 info->ndcb2 = 0; in prepare_set_command()
1099 info->ndcb0 |= NDCB0_CMD_TYPE(5) in prepare_set_command()
1110 dev_err(&info->pdev->dev, "non-supported command %x\n", in prepare_set_command()
1122 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc() local
1130 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc()
1138 if (info->cs != host->cs) { in nand_cmdfunc()
1139 info->cs = host->cs; in nand_cmdfunc()
1140 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
1141 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc()
1144 prepare_start_command(info, command); in nand_cmdfunc()
1146 info->state = STATE_PREPARED; in nand_cmdfunc()
1147 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); in nand_cmdfunc()
1150 init_completion(&info->cmd_complete); in nand_cmdfunc()
1151 init_completion(&info->dev_ready); in nand_cmdfunc()
1152 info->need_wait = 1; in nand_cmdfunc()
1153 pxa3xx_nand_start(info); in nand_cmdfunc()
1155 if (!wait_for_completion_timeout(&info->cmd_complete, in nand_cmdfunc()
1157 dev_err(&info->pdev->dev, "Wait time out!!!\n"); in nand_cmdfunc()
1159 pxa3xx_nand_stop(info); in nand_cmdfunc()
1162 info->state = STATE_IDLE; in nand_cmdfunc()
1170 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc_extended() local
1178 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc_extended()
1186 if (info->cs != host->cs) { in nand_cmdfunc_extended()
1187 info->cs = host->cs; in nand_cmdfunc_extended()
1188 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
1189 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc_extended()
1209 prepare_start_command(info, command); in nand_cmdfunc_extended()
1219 info->need_wait = 1; in nand_cmdfunc_extended()
1220 init_completion(&info->dev_ready); in nand_cmdfunc_extended()
1222 info->state = STATE_PREPARED; in nand_cmdfunc_extended()
1223 exec_cmd = prepare_set_command(info, command, ext_cmd_type, in nand_cmdfunc_extended()
1226 info->need_wait = 0; in nand_cmdfunc_extended()
1227 complete(&info->dev_ready); in nand_cmdfunc_extended()
1231 init_completion(&info->cmd_complete); in nand_cmdfunc_extended()
1232 pxa3xx_nand_start(info); in nand_cmdfunc_extended()
1234 if (!wait_for_completion_timeout(&info->cmd_complete, in nand_cmdfunc_extended()
1236 dev_err(&info->pdev->dev, "Wait time out!!!\n"); in nand_cmdfunc_extended()
1238 pxa3xx_nand_stop(info); in nand_cmdfunc_extended()
1243 if (info->data_size == 0 && command != NAND_CMD_PAGEPROG) in nand_cmdfunc_extended()
1250 if (info->data_size == 0 && in nand_cmdfunc_extended()
1257 if (info->data_size == info->chunk_size) in nand_cmdfunc_extended()
1267 info->data_size == 0) { in nand_cmdfunc_extended()
1272 info->state = STATE_IDLE; in nand_cmdfunc_extended()
1290 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_hwecc() local
1295 if (info->retcode == ERR_CORERR && info->use_ecc) { in pxa3xx_nand_read_page_hwecc()
1296 mtd->ecc_stats.corrected += info->ecc_err_cnt; in pxa3xx_nand_read_page_hwecc()
1298 } else if (info->retcode == ERR_UNCORERR) { in pxa3xx_nand_read_page_hwecc()
1305 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1310 return info->max_bitflips; in pxa3xx_nand_read_page_hwecc()
1316 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_byte() local
1319 if (info->buf_start < info->buf_count) in pxa3xx_nand_read_byte()
1321 retval = info->data_buff[info->buf_start++]; in pxa3xx_nand_read_byte()
1329 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_word() local
1332 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { in pxa3xx_nand_read_word()
1333 retval = *((u16 *)(info->data_buff+info->buf_start)); in pxa3xx_nand_read_word()
1334 info->buf_start += 2; in pxa3xx_nand_read_word()
1342 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_buf() local
1343 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_read_buf()
1345 memcpy(buf, info->data_buff + info->buf_start, real_len); in pxa3xx_nand_read_buf()
1346 info->buf_start += real_len; in pxa3xx_nand_read_buf()
1353 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_write_buf() local
1354 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_write_buf()
1356 memcpy(info->data_buff + info->buf_start, buf, real_len); in pxa3xx_nand_write_buf()
1357 info->buf_start += real_len; in pxa3xx_nand_write_buf()
1368 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_waitfunc() local
1370 if (info->need_wait) { in pxa3xx_nand_waitfunc()
1371 info->need_wait = 0; in pxa3xx_nand_waitfunc()
1372 if (!wait_for_completion_timeout(&info->dev_ready, in pxa3xx_nand_waitfunc()
1374 dev_err(&info->pdev->dev, "Ready time out!!!\n"); in pxa3xx_nand_waitfunc()
1381 if (info->retcode == ERR_NONE) in pxa3xx_nand_waitfunc()
1390 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info) in pxa3xx_nand_config_flash() argument
1392 struct platform_device *pdev = info->pdev; in pxa3xx_nand_config_flash()
1394 struct pxa3xx_nand_host *host = info->host[info->cs]; in pxa3xx_nand_config_flash()
1399 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_config_flash()
1400 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_config_flash()
1401 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); in pxa3xx_nand_config_flash()
1402 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ in pxa3xx_nand_config_flash()
1403 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; in pxa3xx_nand_config_flash()
1404 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; in pxa3xx_nand_config_flash()
1405 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; in pxa3xx_nand_config_flash()
1410 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) in pxa3xx_nand_detect_config() argument
1412 uint32_t ndcr = nand_readl(info, NDCR); in pxa3xx_nand_detect_config()
1415 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; in pxa3xx_nand_detect_config()
1416 info->reg_ndcr = ndcr & in pxa3xx_nand_detect_config()
1418 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
1419 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); in pxa3xx_nand_detect_config()
1423 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_init_buff() argument
1425 struct platform_device *pdev = info->pdev; in pxa3xx_nand_init_buff()
1431 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1432 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1441 sg_init_one(&info->sg, info->data_buff, info->buf_size); in pxa3xx_nand_init_buff()
1445 param.drcmr = info->drcmr_dat; in pxa3xx_nand_init_buff()
1446 info->dma_chan = dma_request_slave_channel_compat(mask, pxad_filter_fn, in pxa3xx_nand_init_buff()
1449 if (!info->dma_chan) { in pxa3xx_nand_init_buff()
1457 config.src_addr = info->mmio_phys + NDDB; in pxa3xx_nand_init_buff()
1458 config.dst_addr = info->mmio_phys + NDDB; in pxa3xx_nand_init_buff()
1461 ret = dmaengine_slave_config(info->dma_chan, &config); in pxa3xx_nand_init_buff()
1463 dev_err(&info->pdev->dev, in pxa3xx_nand_init_buff()
1473 info->use_dma = 1; in pxa3xx_nand_init_buff()
1477 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_free_buff() argument
1479 if (info->use_dma) { in pxa3xx_nand_free_buff()
1480 dmaengine_terminate_all(info->dma_chan); in pxa3xx_nand_free_buff()
1481 dma_release_channel(info->dma_chan); in pxa3xx_nand_free_buff()
1483 kfree(info->data_buff); in pxa3xx_nand_free_buff()
1488 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_sensing() local
1494 mtd = info->host[info->cs]->mtd; in pxa3xx_nand_sensing()
1512 static int pxa_ecc_init(struct pxa3xx_nand_info *info, in pxa_ecc_init() argument
1517 info->chunk_size = 2048; in pxa_ecc_init()
1518 info->spare_size = 40; in pxa_ecc_init()
1519 info->ecc_size = 24; in pxa_ecc_init()
1525 info->chunk_size = 512; in pxa_ecc_init()
1526 info->spare_size = 8; in pxa_ecc_init()
1527 info->ecc_size = 8; in pxa_ecc_init()
1537 info->ecc_bch = 1; in pxa_ecc_init()
1538 info->chunk_size = 2048; in pxa_ecc_init()
1539 info->spare_size = 32; in pxa_ecc_init()
1540 info->ecc_size = 32; in pxa_ecc_init()
1542 ecc->size = info->chunk_size; in pxa_ecc_init()
1547 info->ecc_bch = 1; in pxa_ecc_init()
1548 info->chunk_size = 2048; in pxa_ecc_init()
1549 info->spare_size = 32; in pxa_ecc_init()
1550 info->ecc_size = 32; in pxa_ecc_init()
1552 ecc->size = info->chunk_size; in pxa_ecc_init()
1561 info->ecc_bch = 1; in pxa_ecc_init()
1562 info->chunk_size = 1024; in pxa_ecc_init()
1563 info->spare_size = 0; in pxa_ecc_init()
1564 info->ecc_size = 32; in pxa_ecc_init()
1566 ecc->size = info->chunk_size; in pxa_ecc_init()
1570 dev_err(&info->pdev->dev, in pxa_ecc_init()
1576 dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n", in pxa_ecc_init()
1584 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_scan() local
1585 struct platform_device *pdev = info->pdev; in pxa3xx_nand_scan()
1591 if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) in pxa3xx_nand_scan()
1595 info->chunk_size = 512; in pxa3xx_nand_scan()
1597 ret = pxa3xx_nand_config_flash(info); in pxa3xx_nand_scan()
1603 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", in pxa3xx_nand_scan()
1604 info->cs); in pxa3xx_nand_scan()
1610 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_scan()
1611 if (info->reg_ndcr & NDCR_DWIDTH_M) in pxa3xx_nand_scan()
1615 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_scan()
1616 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_scan()
1624 dev_err(&info->pdev->dev, "Failed to init nand: %d\n", in pxa3xx_nand_scan()
1647 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { in pxa3xx_nand_scan()
1650 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1670 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, in pxa3xx_nand_scan()
1682 kfree(info->data_buff); in pxa3xx_nand_scan()
1685 info->buf_size = mtd->writesize + mtd->oobsize; in pxa3xx_nand_scan()
1686 ret = pxa3xx_nand_init_buff(info); in pxa3xx_nand_scan()
1689 info->oob_buff = info->data_buff + mtd->writesize; in pxa3xx_nand_scan()
1701 struct pxa3xx_nand_info *info; in alloc_nand_resource() local
1711 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + in alloc_nand_resource()
1713 if (!info) in alloc_nand_resource()
1716 info->pdev = pdev; in alloc_nand_resource()
1717 info->variant = pxa3xx_nand_get_variant(pdev); in alloc_nand_resource()
1719 mtd = (void *)&info[1] + (sizeof(*mtd) + sizeof(*host)) * cs; in alloc_nand_resource()
1722 info->host[cs] = host; in alloc_nand_resource()
1725 host->info_data = info; in alloc_nand_resource()
1731 chip->controller = &info->controller; in alloc_nand_resource()
1744 info->clk = devm_clk_get(&pdev->dev, NULL); in alloc_nand_resource()
1745 if (IS_ERR(info->clk)) { in alloc_nand_resource()
1747 return PTR_ERR(info->clk); in alloc_nand_resource()
1749 ret = clk_prepare_enable(info->clk); in alloc_nand_resource()
1761 info->drcmr_dat = r->start; in alloc_nand_resource()
1770 info->drcmr_cmd = r->start; in alloc_nand_resource()
1781 info->mmio_base = devm_ioremap_resource(&pdev->dev, r); in alloc_nand_resource()
1782 if (IS_ERR(info->mmio_base)) { in alloc_nand_resource()
1783 ret = PTR_ERR(info->mmio_base); in alloc_nand_resource()
1786 info->mmio_phys = r->start; in alloc_nand_resource()
1789 info->buf_size = INIT_BUFFER_SIZE; in alloc_nand_resource()
1790 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in alloc_nand_resource()
1791 if (info->data_buff == NULL) { in alloc_nand_resource()
1797 disable_int(info, NDSR_MASK); in alloc_nand_resource()
1801 pdev->name, info); in alloc_nand_resource()
1807 platform_set_drvdata(pdev, info); in alloc_nand_resource()
1812 free_irq(irq, info); in alloc_nand_resource()
1813 kfree(info->data_buff); in alloc_nand_resource()
1815 clk_disable_unprepare(info->clk); in alloc_nand_resource()
1821 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); in pxa3xx_nand_remove() local
1825 if (!info) in pxa3xx_nand_remove()
1832 free_irq(irq, info); in pxa3xx_nand_remove()
1833 pxa3xx_nand_free_buff(info); in pxa3xx_nand_remove()
1842 nand_writel(info, NDCR, in pxa3xx_nand_remove()
1843 (nand_readl(info, NDCR) & ~NDCR_ND_ARB_EN) | in pxa3xx_nand_remove()
1845 clk_disable_unprepare(info->clk); in pxa3xx_nand_remove()
1848 nand_release(info->host[cs]->mtd); in pxa3xx_nand_remove()
1890 struct pxa3xx_nand_info *info; in pxa3xx_nand_probe() local
1917 info = platform_get_drvdata(pdev); in pxa3xx_nand_probe()
1920 struct mtd_info *mtd = info->host[cs]->mtd; in pxa3xx_nand_probe()
1928 info->cs = cs; in pxa3xx_nand_probe()
1955 struct pxa3xx_nand_info *info = dev_get_drvdata(dev); in pxa3xx_nand_suspend() local
1957 if (info->state) { in pxa3xx_nand_suspend()
1958 dev_err(dev, "driver busy, state = %d\n", info->state); in pxa3xx_nand_suspend()
1967 struct pxa3xx_nand_info *info = dev_get_drvdata(dev); in pxa3xx_nand_resume() local
1970 disable_int(info, NDCR_INT_MASK); in pxa3xx_nand_resume()
1977 info->cs = 0xff; in pxa3xx_nand_resume()
1985 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_resume()