55 #define NDCR		(0x00) /* Control register */  macro
589 	nand_writel(info, NDCR, 0);  in pxa3xx_nand_start()
590 	nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_start()
599 	ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
601 		ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_stop()
607 		nand_writel(info, NDCR, ndcr);  in pxa3xx_nand_stop()
621 	ndcr = nand_readl(info, NDCR);  in enable_int()
622 	nand_writel(info, NDCR, ndcr & ~int_mask);  in enable_int()
629 	ndcr = nand_readl(info, NDCR);  in disable_int()
630 	nand_writel(info, NDCR, ndcr | int_mask);  in disable_int()
1412 	uint32_t ndcr = nand_readl(info, NDCR);  in pxa3xx_nand_detect_config()
1842 	nand_writel(info, NDCR,  in pxa3xx_nand_remove()
1843 		    (nand_readl(info, NDCR) & ~NDCR_ND_ARB_EN) |  in pxa3xx_nand_remove()