381 		pc = readl(FSMC_NAND_REG(regs, bank, PC));  in fsmc_cmd_ctrl()
386 		writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));  in fsmc_cmd_ctrl()
430 				FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
433 				FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
435 	writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,  in fsmc_nand_setup()
436 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_nand_setup()
438 			FSMC_NAND_REG(regs, bank, COMM));  in fsmc_nand_setup()
440 			FSMC_NAND_REG(regs, bank, ATTRIB));  in fsmc_nand_setup()
453 	writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,  in fsmc_enable_hwecc()
454 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
455 	writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,  in fsmc_enable_hwecc()
456 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
457 	writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,  in fsmc_enable_hwecc()
458 			FSMC_NAND_REG(regs, bank, PC));  in fsmc_enable_hwecc()
477 		if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)  in fsmc_read_hwecc_ecc4()
488 	ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_read_hwecc_ecc4()
494 	ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));  in fsmc_read_hwecc_ecc4()
500 	ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));  in fsmc_read_hwecc_ecc4()
506 	ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));  in fsmc_read_hwecc_ecc4()
526 	ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_read_hwecc_ecc1()
794 	num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;  in fsmc_bch8_correct_data()
837 	ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));  in fsmc_bch8_correct_data()
838 	ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));  in fsmc_bch8_correct_data()
839 	ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));  in fsmc_bch8_correct_data()
840 	ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));  in fsmc_bch8_correct_data()