161 		out_be32(&lbc->fbar, page_addr >> 6);  in set_addr()
162 		out_be32(&lbc->fpar,  in set_addr()
171 		out_be32(&lbc->fbar, page_addr >> 5);  in set_addr()
172 		out_be32(&lbc->fpar,  in set_addr()
205 	out_be32(&lbc->fmr, priv->fmr | 3);  in fsl_elbc_run_command()
207 		out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);  in fsl_elbc_run_command()
220 	out_be32(&lbc->lsor, priv->bank);  in fsl_elbc_run_command()
259 			out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */  in fsl_elbc_run_command()
276 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
283 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |  in fsl_elbc_do_read()
286 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
293 			out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
295 			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
328 		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */  in fsl_elbc_cmdfunc()
344 		out_be32(&lbc->fbcr, mtd->oobsize - column);  in fsl_elbc_cmdfunc()
357 		out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |  in fsl_elbc_cmdfunc()
360 		out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
365 		out_be32(&lbc->fbcr, 256);  in fsl_elbc_cmdfunc()
385 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
392 		out_be32(&lbc->fcr,  in fsl_elbc_cmdfunc()
397 		out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
429 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
438 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
456 		out_be32(&lbc->fcr, fcr);  in fsl_elbc_cmdfunc()
473 			out_be32(&lbc->fbcr,  in fsl_elbc_cmdfunc()
476 			out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
485 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
488 		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
489 		out_be32(&lbc->fbcr, 1);  in fsl_elbc_cmdfunc()
504 		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);  in fsl_elbc_cmdfunc()
505 		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()