106 							uint32_t irq_mask);
165 	uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;  in reset_bank()  local
171 	irq_status = wait_for_irq(denali, irq_mask);  in reset_bank()
628 							uint32_t irq_mask)  in clear_interrupt()  argument
634 	iowrite32(irq_mask, denali->flash_reg + intr_status_reg);  in clear_interrupt()
698 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)  in wait_for_irq()  argument
710 		if (intr_status & irq_mask) {  in wait_for_irq()
711 			denali->irq_status &= ~irq_mask;  in wait_for_irq()
727 				intr_status, irq_mask);  in wait_for_irq()
762 	uint32_t addr, cmd, irq_status, irq_mask;  in denali_send_pipeline_cmd()  local
765 		irq_mask = INTR_STATUS__LOAD_COMP;  in denali_send_pipeline_cmd()
767 		irq_mask = 0;  in denali_send_pipeline_cmd()
809 			irq_status = wait_for_irq(denali, irq_mask);  in denali_send_pipeline_cmd()
872 	uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |  in write_oob_data()  local
883 		irq_status = wait_for_irq(denali, irq_mask);  in write_oob_data()
900 	uint32_t irq_mask = INTR_STATUS__LOAD_COMP;  in read_oob_data()  local
914 		irq_status = wait_for_irq(denali, irq_mask);  in read_oob_data()
1067 	uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |  in write_page()  local
1095 	irq_status = wait_for_irq(denali, irq_mask);  in write_page()
1166 	uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |  in denali_read_page()  local
1186 	irq_status = wait_for_irq(denali, irq_mask);  in denali_read_page()
1215 	uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;  in denali_read_page_raw()  local
1233 	wait_for_irq(denali, irq_mask);  in denali_read_page_raw()