Lines Matching refs:sample
220 u32 sample; member
669 sclk_dly = host->clk_delays[SDXC_CLK_400K].sample; in sunxi_mmc_clk_set_rate()
672 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample; in sunxi_mmc_clk_set_rate()
676 sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample; in sunxi_mmc_clk_set_rate()
679 sclk_dly = host->clk_delays[SDXC_CLK_50M].sample; in sunxi_mmc_clk_set_rate()
902 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
903 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
904 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
905 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
909 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
910 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
911 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
912 [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 },