264 	u32 rval;  in sunxi_mmc_reset_host()  local
268 		rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_reset_host()
269 	} while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));  in sunxi_mmc_reset_host()
271 	if (rval & SDXC_HARDWARE_RESET) {  in sunxi_mmc_reset_host()
281 	u32 rval;  in sunxi_mmc_init_host()  local
295 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_init_host()
296 	rval |= SDXC_INTERRUPT_ENABLE_BIT;  in sunxi_mmc_init_host()
297 	rval &= ~SDXC_ACCESS_DONE_DIRECT;  in sunxi_mmc_init_host()
298 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_init_host()
372 	u32 rval;  in sunxi_mmc_start_dma()  local
376 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_start_dma()
377 	rval |= SDXC_DMA_ENABLE_BIT;  in sunxi_mmc_start_dma()
378 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_start_dma()
379 	rval |= SDXC_DMA_RESET;  in sunxi_mmc_start_dma()
380 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_start_dma()
461 	u32 rval;  in sunxi_mmc_finalize_request()  local
494 		rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_finalize_request()
495 		rval |= SDXC_DMA_RESET;  in sunxi_mmc_finalize_request()
496 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
497 		rval &= ~SDXC_DMA_ENABLE_BIT;  in sunxi_mmc_finalize_request()
498 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
499 		rval |= SDXC_FIFO_RESET;  in sunxi_mmc_finalize_request()
500 		mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_finalize_request()
610 	u32 rval;  in sunxi_mmc_oclk_onoff()  local
612 	rval = mmc_readl(host, REG_CLKCR);  in sunxi_mmc_oclk_onoff()
613 	rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);  in sunxi_mmc_oclk_onoff()
616 		rval |= SDXC_CARD_CLOCK_ON;  in sunxi_mmc_oclk_onoff()
618 	mmc_writel(host, REG_CLKCR, rval);  in sunxi_mmc_oclk_onoff()
620 	rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;  in sunxi_mmc_oclk_onoff()
621 	mmc_writel(host, REG_CMDR, rval);  in sunxi_mmc_oclk_onoff()
624 		rval = mmc_readl(host, REG_CMDR);  in sunxi_mmc_oclk_onoff()
625 	} while (time_before(jiffies, expire) && (rval & SDXC_START));  in sunxi_mmc_oclk_onoff()
631 	if (rval & SDXC_START) {  in sunxi_mmc_oclk_onoff()
642 	u32 rate, oclk_dly, rval, sclk_dly;  in sunxi_mmc_clk_set_rate()  local
662 	rval = mmc_readl(host, REG_CLKCR);  in sunxi_mmc_clk_set_rate()
663 	rval &= ~0xff;  in sunxi_mmc_clk_set_rate()
664 	mmc_writel(host, REG_CLKCR, rval);  in sunxi_mmc_clk_set_rate()
694 	u32 rval;  in sunxi_mmc_set_ios()  local
732 	rval = mmc_readl(host, REG_GCTRL);  in sunxi_mmc_set_ios()
734 		rval |= SDXC_DDR_MODE;  in sunxi_mmc_set_ios()
736 		rval &= ~SDXC_DDR_MODE;  in sunxi_mmc_set_ios()
737 	mmc_writel(host, REG_GCTRL, rval);  in sunxi_mmc_set_ios()