Lines Matching refs:host
270 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) argument
272 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, in sh_mmcif_bitset() argument
275 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
278 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, in sh_mmcif_bitclr() argument
281 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
286 struct sh_mmcif_host *host = arg; in sh_mmcif_dma_complete() local
287 struct mmc_request *mrq = host->mrq; in sh_mmcif_dma_complete()
288 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_dma_complete()
296 complete(&host->dma_complete); in sh_mmcif_dma_complete()
299 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_rx() argument
301 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_rx()
304 struct dma_chan *chan = host->chan_rx; in sh_mmcif_start_dma_rx()
305 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_rx()
312 host->dma_active = true; in sh_mmcif_start_dma_rx()
319 desc->callback_param = host; in sh_mmcif_start_dma_rx()
321 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); in sh_mmcif_start_dma_rx()
331 host->chan_rx = NULL; in sh_mmcif_start_dma_rx()
332 host->dma_active = false; in sh_mmcif_start_dma_rx()
335 chan = host->chan_tx; in sh_mmcif_start_dma_rx()
337 host->chan_tx = NULL; in sh_mmcif_start_dma_rx()
342 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_rx()
349 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_tx() argument
351 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_tx()
354 struct dma_chan *chan = host->chan_tx; in sh_mmcif_start_dma_tx()
355 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_tx()
362 host->dma_active = true; in sh_mmcif_start_dma_tx()
369 desc->callback_param = host; in sh_mmcif_start_dma_tx()
371 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
381 host->chan_tx = NULL; in sh_mmcif_start_dma_tx()
382 host->dma_active = false; in sh_mmcif_start_dma_tx()
385 chan = host->chan_rx; in sh_mmcif_start_dma_tx()
387 host->chan_rx = NULL; in sh_mmcif_start_dma_tx()
392 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
400 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) in sh_mmcif_request_dma_pdata() argument
412 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, in sh_mmcif_dma_slave_config() argument
419 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); in sh_mmcif_dma_slave_config()
433 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) in sh_mmcif_request_dma() argument
435 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request_dma()
436 host->dma_active = false; in sh_mmcif_request_dma()
442 host->chan_tx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
444 host->chan_rx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
447 host->chan_tx = dma_request_slave_channel(dev, "tx"); in sh_mmcif_request_dma()
448 host->chan_rx = dma_request_slave_channel(dev, "rx"); in sh_mmcif_request_dma()
450 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, in sh_mmcif_request_dma()
451 host->chan_rx); in sh_mmcif_request_dma()
453 if (!host->chan_tx || !host->chan_rx || in sh_mmcif_request_dma()
454 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || in sh_mmcif_request_dma()
455 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) in sh_mmcif_request_dma()
461 if (host->chan_tx) in sh_mmcif_request_dma()
462 dma_release_channel(host->chan_tx); in sh_mmcif_request_dma()
463 if (host->chan_rx) in sh_mmcif_request_dma()
464 dma_release_channel(host->chan_rx); in sh_mmcif_request_dma()
465 host->chan_tx = host->chan_rx = NULL; in sh_mmcif_request_dma()
468 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) in sh_mmcif_release_dma() argument
470 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_release_dma()
472 if (host->chan_tx) { in sh_mmcif_release_dma()
473 struct dma_chan *chan = host->chan_tx; in sh_mmcif_release_dma()
474 host->chan_tx = NULL; in sh_mmcif_release_dma()
477 if (host->chan_rx) { in sh_mmcif_release_dma()
478 struct dma_chan *chan = host->chan_rx; in sh_mmcif_release_dma()
479 host->chan_rx = NULL; in sh_mmcif_release_dma()
483 host->dma_active = false; in sh_mmcif_release_dma()
486 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) in sh_mmcif_clock_control() argument
488 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clock_control()
491 unsigned int current_clk = clk_get_rate(host->clk); in sh_mmcif_clock_control()
494 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
495 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); in sh_mmcif_clock_control()
500 if (host->clkdiv_map) { in sh_mmcif_clock_control()
508 if (!((1 << i) & host->clkdiv_map)) in sh_mmcif_clock_control()
517 freq = clk_round_rate(host->clk, clk * div); in sh_mmcif_clock_control()
532 clk_set_rate(host->clk, best_freq); in sh_mmcif_clock_control()
540 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
541 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
544 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) in sh_mmcif_sync_reset() argument
548 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); in sh_mmcif_sync_reset()
550 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); in sh_mmcif_sync_reset()
551 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); in sh_mmcif_sync_reset()
552 if (host->ccs_enable) in sh_mmcif_sync_reset()
554 if (host->clk_ctrl2_enable) in sh_mmcif_sync_reset()
555 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); in sh_mmcif_sync_reset()
556 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | in sh_mmcif_sync_reset()
559 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); in sh_mmcif_sync_reset()
562 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) in sh_mmcif_error_manage() argument
564 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_error_manage()
568 host->sd_error = false; in sh_mmcif_error_manage()
570 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); in sh_mmcif_error_manage()
571 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); in sh_mmcif_error_manage()
576 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); in sh_mmcif_error_manage()
577 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); in sh_mmcif_error_manage()
579 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) in sh_mmcif_error_manage()
589 sh_mmcif_sync_reset(host); in sh_mmcif_error_manage()
596 host->state, host->wait_for); in sh_mmcif_error_manage()
600 host->state, host->wait_for); in sh_mmcif_error_manage()
604 host->state, host->wait_for); in sh_mmcif_error_manage()
610 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) in sh_mmcif_next_block() argument
612 struct mmc_data *data = host->mrq->data; in sh_mmcif_next_block()
614 host->sg_blkidx += host->blocksize; in sh_mmcif_next_block()
617 BUG_ON(host->sg_blkidx > data->sg->length); in sh_mmcif_next_block()
619 if (host->sg_blkidx == data->sg->length) { in sh_mmcif_next_block()
620 host->sg_blkidx = 0; in sh_mmcif_next_block()
621 if (++host->sg_idx < data->sg_len) in sh_mmcif_next_block()
622 host->pio_ptr = sg_virt(++data->sg); in sh_mmcif_next_block()
624 host->pio_ptr = p; in sh_mmcif_next_block()
627 return host->sg_idx != data->sg_len; in sh_mmcif_next_block()
630 static void sh_mmcif_single_read(struct sh_mmcif_host *host, in sh_mmcif_single_read() argument
633 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_read()
636 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
639 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_single_read()
642 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) in sh_mmcif_read_block() argument
644 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_read_block()
645 struct mmc_data *data = host->mrq->data; in sh_mmcif_read_block()
649 if (host->sd_error) { in sh_mmcif_read_block()
650 data->error = sh_mmcif_error_manage(host); in sh_mmcif_read_block()
655 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_read_block()
656 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_read_block()
659 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); in sh_mmcif_read_block()
660 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
665 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, in sh_mmcif_multi_read() argument
673 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_read()
676 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
677 host->sg_idx = 0; in sh_mmcif_multi_read()
678 host->sg_blkidx = 0; in sh_mmcif_multi_read()
679 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_read()
681 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_multi_read()
684 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) in sh_mmcif_mread_block() argument
686 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mread_block()
687 struct mmc_data *data = host->mrq->data; in sh_mmcif_mread_block()
688 u32 *p = host->pio_ptr; in sh_mmcif_mread_block()
691 if (host->sd_error) { in sh_mmcif_mread_block()
692 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mread_block()
699 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mread_block()
700 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_mread_block()
702 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mread_block()
705 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_mread_block()
710 static void sh_mmcif_single_write(struct sh_mmcif_host *host, in sh_mmcif_single_write() argument
713 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_write()
716 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
719 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_single_write()
722 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) in sh_mmcif_write_block() argument
724 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_write_block()
725 struct mmc_data *data = host->mrq->data; in sh_mmcif_write_block()
729 if (host->sd_error) { in sh_mmcif_write_block()
730 data->error = sh_mmcif_error_manage(host); in sh_mmcif_write_block()
735 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_write_block()
736 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_write_block()
739 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); in sh_mmcif_write_block()
740 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
745 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, in sh_mmcif_multi_write() argument
753 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_write()
756 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
757 host->sg_idx = 0; in sh_mmcif_multi_write()
758 host->sg_blkidx = 0; in sh_mmcif_multi_write()
759 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_write()
761 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_multi_write()
764 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) in sh_mmcif_mwrite_block() argument
766 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mwrite_block()
767 struct mmc_data *data = host->mrq->data; in sh_mmcif_mwrite_block()
768 u32 *p = host->pio_ptr; in sh_mmcif_mwrite_block()
771 if (host->sd_error) { in sh_mmcif_mwrite_block()
772 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mwrite_block()
779 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mwrite_block()
780 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_mwrite_block()
782 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mwrite_block()
785 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_mwrite_block()
790 static void sh_mmcif_get_response(struct sh_mmcif_host *host, in sh_mmcif_get_response() argument
794 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); in sh_mmcif_get_response()
795 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); in sh_mmcif_get_response()
796 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); in sh_mmcif_get_response()
797 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
799 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
802 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, in sh_mmcif_get_cmd12response() argument
805 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); in sh_mmcif_get_cmd12response()
808 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, in sh_mmcif_set_cmd() argument
811 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_cmd()
848 switch (host->bus_width) { in sh_mmcif_set_cmd()
862 switch (host->timing) { in sh_mmcif_set_cmd()
881 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, in sh_mmcif_set_cmd()
899 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, in sh_mmcif_data_trans() argument
902 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_data_trans()
906 sh_mmcif_multi_read(host, mrq); in sh_mmcif_data_trans()
909 sh_mmcif_multi_write(host, mrq); in sh_mmcif_data_trans()
912 sh_mmcif_single_write(host, mrq); in sh_mmcif_data_trans()
916 sh_mmcif_single_read(host, mrq); in sh_mmcif_data_trans()
924 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, in sh_mmcif_start_cmd() argument
947 if (host->ccs_enable) in sh_mmcif_start_cmd()
951 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); in sh_mmcif_start_cmd()
952 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, in sh_mmcif_start_cmd()
955 opc = sh_mmcif_set_cmd(host, mrq); in sh_mmcif_start_cmd()
957 if (host->ccs_enable) in sh_mmcif_start_cmd()
958 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); in sh_mmcif_start_cmd()
960 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); in sh_mmcif_start_cmd()
961 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); in sh_mmcif_start_cmd()
963 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); in sh_mmcif_start_cmd()
965 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_start_cmd()
966 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); in sh_mmcif_start_cmd()
968 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
969 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_start_cmd()
970 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_start_cmd()
973 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, in sh_mmcif_stop_cmd() argument
976 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_stop_cmd()
980 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); in sh_mmcif_stop_cmd()
983 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); in sh_mmcif_stop_cmd()
987 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_stop_cmd()
991 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
996 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_request() local
997 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request()
1000 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_request()
1001 if (host->state != STATE_IDLE) { in sh_mmcif_request()
1003 __func__, host->state); in sh_mmcif_request()
1004 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1010 host->state = STATE_REQUEST; in sh_mmcif_request()
1011 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1021 host->state = STATE_IDLE; in sh_mmcif_request()
1029 host->mrq = mrq; in sh_mmcif_request()
1031 sh_mmcif_start_cmd(host, mrq); in sh_mmcif_request()
1034 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) in sh_mmcif_clk_setup() argument
1036 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clk_setup()
1038 if (host->mmc->f_max) { in sh_mmcif_clk_setup()
1041 f_max = host->mmc->f_max; in sh_mmcif_clk_setup()
1043 f_min = clk_round_rate(host->clk, f_min_old / 2); in sh_mmcif_clk_setup()
1052 host->clkdiv_map = 0x3ff; in sh_mmcif_clk_setup()
1054 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); in sh_mmcif_clk_setup()
1055 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); in sh_mmcif_clk_setup()
1057 unsigned int clk = clk_get_rate(host->clk); in sh_mmcif_clk_setup()
1059 host->mmc->f_max = clk / 2; in sh_mmcif_clk_setup()
1060 host->mmc->f_min = clk / 512; in sh_mmcif_clk_setup()
1064 host->mmc->f_max, host->mmc->f_min); in sh_mmcif_clk_setup()
1067 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) in sh_mmcif_set_power() argument
1069 struct mmc_host *mmc = host->mmc; in sh_mmcif_set_power()
1079 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_set_ios() local
1080 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_ios()
1083 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_set_ios()
1084 if (host->state != STATE_IDLE) { in sh_mmcif_set_ios()
1086 __func__, host->state); in sh_mmcif_set_ios()
1087 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1091 host->state = STATE_IOS; in sh_mmcif_set_ios()
1092 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1095 if (!host->card_present) { in sh_mmcif_set_ios()
1097 sh_mmcif_request_dma(host); in sh_mmcif_set_ios()
1098 host->card_present = true; in sh_mmcif_set_ios()
1100 sh_mmcif_set_power(host, ios); in sh_mmcif_set_ios()
1103 sh_mmcif_clock_control(host, 0); in sh_mmcif_set_ios()
1105 if (host->card_present) { in sh_mmcif_set_ios()
1106 sh_mmcif_release_dma(host); in sh_mmcif_set_ios()
1107 host->card_present = false; in sh_mmcif_set_ios()
1110 if (host->power) { in sh_mmcif_set_ios()
1112 clk_disable_unprepare(host->clk); in sh_mmcif_set_ios()
1113 host->power = false; in sh_mmcif_set_ios()
1115 sh_mmcif_set_power(host, ios); in sh_mmcif_set_ios()
1117 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1122 if (!host->power) { in sh_mmcif_set_ios()
1123 clk_prepare_enable(host->clk); in sh_mmcif_set_ios()
1126 host->power = true; in sh_mmcif_set_ios()
1127 sh_mmcif_sync_reset(host); in sh_mmcif_set_ios()
1129 sh_mmcif_clock_control(host, ios->clock); in sh_mmcif_set_ios()
1132 host->timing = ios->timing; in sh_mmcif_set_ios()
1133 host->bus_width = ios->bus_width; in sh_mmcif_set_ios()
1134 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1139 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_get_cd() local
1140 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_get_cd()
1150 return p->get_cd(host->pd); in sh_mmcif_get_cd()
1159 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) in sh_mmcif_end_cmd() argument
1161 struct mmc_command *cmd = host->mrq->cmd; in sh_mmcif_end_cmd()
1162 struct mmc_data *data = host->mrq->data; in sh_mmcif_end_cmd()
1163 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_end_cmd()
1166 if (host->sd_error) { in sh_mmcif_end_cmd()
1174 cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1179 host->sd_error = false; in sh_mmcif_end_cmd()
1187 sh_mmcif_get_response(host, cmd); in sh_mmcif_end_cmd()
1196 init_completion(&host->dma_complete); in sh_mmcif_end_cmd()
1199 if (host->chan_rx) in sh_mmcif_end_cmd()
1200 sh_mmcif_start_dma_rx(host); in sh_mmcif_end_cmd()
1202 if (host->chan_tx) in sh_mmcif_end_cmd()
1203 sh_mmcif_start_dma_tx(host); in sh_mmcif_end_cmd()
1206 if (!host->dma_active) { in sh_mmcif_end_cmd()
1207 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); in sh_mmcif_end_cmd()
1212 time = wait_for_completion_interruptible_timeout(&host->dma_complete, in sh_mmcif_end_cmd()
1213 host->timeout); in sh_mmcif_end_cmd()
1216 dma_unmap_sg(host->chan_rx->device->dev, in sh_mmcif_end_cmd()
1220 dma_unmap_sg(host->chan_tx->device->dev, in sh_mmcif_end_cmd()
1224 if (host->sd_error) { in sh_mmcif_end_cmd()
1225 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1228 data->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1230 dev_err(host->mmc->parent, "DMA timeout!\n"); in sh_mmcif_end_cmd()
1233 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1237 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, in sh_mmcif_end_cmd()
1239 host->dma_active = false; in sh_mmcif_end_cmd()
1245 dmaengine_terminate_all(host->chan_rx); in sh_mmcif_end_cmd()
1247 dmaengine_terminate_all(host->chan_tx); in sh_mmcif_end_cmd()
1255 struct sh_mmcif_host *host = dev_id; in sh_mmcif_irqt() local
1257 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_irqt()
1262 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_irqt()
1263 wait_work = host->wait_for; in sh_mmcif_irqt()
1264 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_irqt()
1266 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_irqt()
1268 mutex_lock(&host->thread_lock); in sh_mmcif_irqt()
1270 mrq = host->mrq; in sh_mmcif_irqt()
1273 host->state, host->wait_for); in sh_mmcif_irqt()
1274 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1285 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1289 wait = sh_mmcif_end_cmd(host); in sh_mmcif_irqt()
1293 wait = sh_mmcif_mread_block(host); in sh_mmcif_irqt()
1297 wait = sh_mmcif_read_block(host); in sh_mmcif_irqt()
1301 wait = sh_mmcif_mwrite_block(host); in sh_mmcif_irqt()
1305 wait = sh_mmcif_write_block(host); in sh_mmcif_irqt()
1308 if (host->sd_error) { in sh_mmcif_irqt()
1309 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1313 sh_mmcif_get_cmd12response(host, mrq->stop); in sh_mmcif_irqt()
1318 if (host->sd_error) { in sh_mmcif_irqt()
1319 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1328 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1330 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1334 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { in sh_mmcif_irqt()
1341 sh_mmcif_stop_cmd(host, mrq); in sh_mmcif_irqt()
1343 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1344 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1350 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_irqt()
1351 host->state = STATE_IDLE; in sh_mmcif_irqt()
1352 host->mrq = NULL; in sh_mmcif_irqt()
1353 mmc_request_done(host->mmc, mrq); in sh_mmcif_irqt()
1355 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1362 struct sh_mmcif_host *host = dev_id; in sh_mmcif_intr() local
1363 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_intr()
1366 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); in sh_mmcif_intr()
1367 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); in sh_mmcif_intr()
1368 if (host->ccs_enable) in sh_mmcif_intr()
1369 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); in sh_mmcif_intr()
1371 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); in sh_mmcif_intr()
1372 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); in sh_mmcif_intr()
1379 host->sd_error = true; in sh_mmcif_intr()
1383 if (!host->mrq) in sh_mmcif_intr()
1385 if (!host->dma_active) in sh_mmcif_intr()
1387 else if (host->sd_error) in sh_mmcif_intr()
1388 sh_mmcif_dma_complete(host); in sh_mmcif_intr()
1399 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); in sh_mmcif_timeout_work() local
1400 struct mmc_request *mrq = host->mrq; in sh_mmcif_timeout_work()
1401 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_timeout_work()
1404 if (host->dying) in sh_mmcif_timeout_work()
1408 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_timeout_work()
1409 if (host->state == STATE_IDLE) { in sh_mmcif_timeout_work()
1410 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1415 host->wait_for, mrq->cmd->opcode); in sh_mmcif_timeout_work()
1417 host->state = STATE_TIMEOUT; in sh_mmcif_timeout_work()
1418 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1424 switch (host->wait_for) { in sh_mmcif_timeout_work()
1426 mrq->cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1429 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1437 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1443 host->state = STATE_IDLE; in sh_mmcif_timeout_work()
1444 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_timeout_work()
1445 host->mrq = NULL; in sh_mmcif_timeout_work()
1446 mmc_request_done(host->mmc, mrq); in sh_mmcif_timeout_work()
1449 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) in sh_mmcif_init_ocr() argument
1451 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_init_ocr()
1453 struct mmc_host *mmc = host->mmc; in sh_mmcif_init_ocr()
1470 struct sh_mmcif_host *host; in sh_mmcif_probe() local
1497 host = mmc_priv(mmc); in sh_mmcif_probe()
1498 host->mmc = mmc; in sh_mmcif_probe()
1499 host->addr = reg; in sh_mmcif_probe()
1500 host->timeout = msecs_to_jiffies(10000); in sh_mmcif_probe()
1501 host->ccs_enable = !pd || !pd->ccs_unsupported; in sh_mmcif_probe()
1502 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; in sh_mmcif_probe()
1504 host->pd = pdev; in sh_mmcif_probe()
1506 spin_lock_init(&host->lock); in sh_mmcif_probe()
1509 sh_mmcif_init_ocr(host); in sh_mmcif_probe()
1520 platform_set_drvdata(pdev, host); in sh_mmcif_probe()
1523 host->power = false; in sh_mmcif_probe()
1525 host->clk = devm_clk_get(dev, NULL); in sh_mmcif_probe()
1526 if (IS_ERR(host->clk)) { in sh_mmcif_probe()
1527 ret = PTR_ERR(host->clk); in sh_mmcif_probe()
1532 ret = clk_prepare_enable(host->clk); in sh_mmcif_probe()
1536 sh_mmcif_clk_setup(host); in sh_mmcif_probe()
1542 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); in sh_mmcif_probe()
1544 sh_mmcif_sync_reset(host); in sh_mmcif_probe()
1545 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_probe()
1549 sh_mmcif_irqt, 0, name, host); in sh_mmcif_probe()
1557 0, "sh_mmc:int", host); in sh_mmcif_probe()
1570 mutex_init(&host->thread_lock); in sh_mmcif_probe()
1579 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, in sh_mmcif_probe()
1580 clk_get_rate(host->clk) / 1000000UL); in sh_mmcif_probe()
1582 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1586 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1596 struct sh_mmcif_host *host = platform_get_drvdata(pdev); in sh_mmcif_remove() local
1598 host->dying = true; in sh_mmcif_remove()
1599 clk_prepare_enable(host->clk); in sh_mmcif_remove()
1604 mmc_remove_host(host->mmc); in sh_mmcif_remove()
1605 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_remove()
1612 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_remove()
1614 clk_disable_unprepare(host->clk); in sh_mmcif_remove()
1615 mmc_free_host(host->mmc); in sh_mmcif_remove()
1625 struct sh_mmcif_host *host = dev_get_drvdata(dev); in sh_mmcif_suspend() local
1628 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_suspend()