Lines Matching refs:ctrl
163 u32 ctrl; in sdhci_s3c_set_clock() local
201 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); in sdhci_s3c_set_clock()
202 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; in sdhci_s3c_set_clock()
203 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; in sdhci_s3c_set_clock()
204 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); in sdhci_s3c_set_clock()
210 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); in sdhci_s3c_set_clock()
211 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | in sdhci_s3c_set_clock()
216 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); in sdhci_s3c_set_clock()
219 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); in sdhci_s3c_set_clock()
221 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); in sdhci_s3c_set_clock()
222 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); in sdhci_s3c_set_clock()
360 u8 ctrl; in sdhci_s3c_set_bus_width() local
362 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); in sdhci_s3c_set_bus_width()
366 ctrl |= SDHCI_CTRL_8BITBUS; in sdhci_s3c_set_bus_width()
367 ctrl &= ~SDHCI_CTRL_4BITBUS; in sdhci_s3c_set_bus_width()
370 ctrl |= SDHCI_CTRL_4BITBUS; in sdhci_s3c_set_bus_width()
371 ctrl &= ~SDHCI_CTRL_8BITBUS; in sdhci_s3c_set_bus_width()
374 ctrl &= ~SDHCI_CTRL_4BITBUS; in sdhci_s3c_set_bus_width()
375 ctrl &= ~SDHCI_CTRL_8BITBUS; in sdhci_s3c_set_bus_width()
379 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); in sdhci_s3c_set_bus_width()