Lines Matching refs:tmp
62 u16 tmp = 0; in pxav2_reset() local
69 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
71 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); in pxav2_reset()
72 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav2_reset()
74 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); in pxav2_reset()
75 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; in pxav2_reset()
77 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
81 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
82 tmp &= ~CLK_GATE_SETTING_BITS; in pxav2_reset()
83 writew(tmp, host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
85 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
86 tmp &= ~CLK_GATE_SETTING_BITS; in pxav2_reset()
87 tmp |= CLK_GATE_SETTING_BITS; in pxav2_reset()
88 writew(tmp, host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
96 u16 tmp; in pxav2_mmc_set_bus_width() local
99 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav2_mmc_set_bus_width()
102 tmp |= MMC_CARD | MMC_WIDTH; in pxav2_mmc_set_bus_width()
104 tmp &= ~(MMC_CARD | MMC_WIDTH); in pxav2_mmc_set_bus_width()
110 writew(tmp, host->ioaddr + SD_CE_ATA_2); in pxav2_mmc_set_bus_width()