49 				     int spec_reg, u32 value)  in esdhc_readl_fixup()  argument
63 	if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {  in esdhc_readl_fixup()
65 			ret = value | SDHCI_CAN_DO_ADMA2;  in esdhc_readl_fixup()
69 	ret = value;  in esdhc_readl_fixup()
74 				     int spec_reg, u32 value)  in esdhc_readw_fixup()  argument
80 		ret = value & 0xffff;  in esdhc_readw_fixup()
82 		ret = (value >> shift) & 0xffff;  in esdhc_readw_fixup()
87 				     int spec_reg, u32 value)  in esdhc_readb_fixup()  argument
93 	ret = (value >> shift) & 0xff;  in esdhc_readb_fixup()
101 		dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;  in esdhc_readb_fixup()
126 				     int spec_reg, u32 value, u32 old_value)  in esdhc_writel_fixup()  argument
136 		ret = value | SDHCI_INT_BLK_GAP;  in esdhc_writel_fixup()
138 		ret = value;  in esdhc_writel_fixup()
144 				     int spec_reg, u16 value, u32 old_value)  in esdhc_writew_fixup()  argument
156 		pltfm_host->xfer_mode_shadow = value;  in esdhc_writew_fixup()
159 		ret = (value << 16) | pltfm_host->xfer_mode_shadow;  in esdhc_writew_fixup()
164 	ret |= (value << shift);  in esdhc_writew_fixup()
178 				     int spec_reg, u8 value, u32 old_value)  in esdhc_writeb_fixup()  argument
204 		dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;  in esdhc_writeb_fixup()
206 		tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |  in esdhc_writeb_fixup()
215 	ret = (old_value & (~(0xff << shift))) | (value << shift);  in esdhc_writeb_fixup()
222 	u32 value;  in esdhc_be_readl()  local
224 	value = ioread32be(host->ioaddr + reg);  in esdhc_be_readl()
225 	ret = esdhc_readl_fixup(host, reg, value);  in esdhc_be_readl()
233 	u32 value;  in esdhc_le_readl()  local
235 	value = ioread32(host->ioaddr + reg);  in esdhc_le_readl()
236 	ret = esdhc_readl_fixup(host, reg, value);  in esdhc_le_readl()
244 	u32 value;  in esdhc_be_readw()  local
247 	value = ioread32be(host->ioaddr + base);  in esdhc_be_readw()
248 	ret = esdhc_readw_fixup(host, reg, value);  in esdhc_be_readw()
255 	u32 value;  in esdhc_le_readw()  local
258 	value = ioread32(host->ioaddr + base);  in esdhc_le_readw()
259 	ret = esdhc_readw_fixup(host, reg, value);  in esdhc_le_readw()
266 	u32 value;  in esdhc_be_readb()  local
269 	value = ioread32be(host->ioaddr + base);  in esdhc_be_readb()
270 	ret = esdhc_readb_fixup(host, reg, value);  in esdhc_be_readb()
277 	u32 value;  in esdhc_le_readb()  local
280 	value = ioread32(host->ioaddr + base);  in esdhc_le_readb()
281 	ret = esdhc_readb_fixup(host, reg, value);  in esdhc_le_readb()
287 	u32 value;  in esdhc_be_writel()  local
289 	value = esdhc_writel_fixup(host, reg, val, 0);  in esdhc_be_writel()
290 	iowrite32be(value, host->ioaddr + reg);  in esdhc_be_writel()
295 	u32 value;  in esdhc_le_writel()  local
297 	value = esdhc_writel_fixup(host, reg, val, 0);  in esdhc_le_writel()
298 	iowrite32(value, host->ioaddr + reg);  in esdhc_le_writel()
304 	u32 value;  in esdhc_be_writew()  local
307 	value = ioread32be(host->ioaddr + base);  in esdhc_be_writew()
308 	ret = esdhc_writew_fixup(host, reg, val, value);  in esdhc_be_writew()
316 	u32 value;  in esdhc_le_writew()  local
319 	value = ioread32(host->ioaddr + base);  in esdhc_le_writew()
320 	ret = esdhc_writew_fixup(host, reg, val, value);  in esdhc_le_writew()
328 	u32 value;  in esdhc_be_writeb()  local
331 	value = ioread32be(host->ioaddr + base);  in esdhc_be_writeb()
332 	ret = esdhc_writeb_fixup(host, reg, val, value);  in esdhc_be_writeb()
339 	u32 value;  in esdhc_le_writeb()  local
342 	value = ioread32(host->ioaddr + base);  in esdhc_le_writeb()
343 	ret = esdhc_writeb_fixup(host, reg, val, value);  in esdhc_le_writeb()
382 	u32 value;  in esdhc_of_enable_dma()  local
384 	value = sdhci_readl(host, ESDHC_DMA_SYSCTL);  in esdhc_of_enable_dma()
385 	value |= ESDHC_DMA_SNOOP;  in esdhc_of_enable_dma()
386 	sdhci_writel(host, value, ESDHC_DMA_SYSCTL);  in esdhc_of_enable_dma()