Lines Matching refs:WRITE_REG_CMD
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, in sd_cmd_set_sd_cmd()
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); in sd_cmd_set_data_len()
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); in sd_cmd_set_data_len()
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); in sd_cmd_set_data_len()
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); in sd_cmd_set_data_len()
260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); in sd_send_cmd_get_rsp()
261 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, in sd_send_cmd_get_rsp()
263 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, in sd_send_cmd_get_rsp()
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, in sd_read_data()
366 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in sd_read_data()
369 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, in sd_read_data()
422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, in sd_write_data()
425 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, in sd_write_data()
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, in sd_read_long_data()
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, in sd_read_long_data()
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, in sd_read_long_data()
474 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, in sd_read_long_data()
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); in sd_read_long_data()
477 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, in sd_read_long_data()
480 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, in sd_read_long_data()
482 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); in sd_read_long_data()
483 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, in sd_read_long_data()
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, in sd_write_long_data()
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, in sd_write_long_data()
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, in sd_write_long_data()
533 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, in sd_write_long_data()
535 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); in sd_write_long_data()
536 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, in sd_write_long_data()
539 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, in sd_write_long_data()
541 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); in sd_write_long_data()
542 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, in sd_write_long_data()
630 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); in sd_change_phase()
632 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in sd_change_phase()
635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in sd_change_phase()
637 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in sd_change_phase()
638 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
640 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); in sd_change_phase()
641 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in sd_change_phase()
917 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); in sd_power_on()
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, in sd_power_on()
920 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, in sd_power_on()
951 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); in sd_power_off()
952 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); in sd_power_off()
988 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
993 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, in sd_set_timing()
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1000 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, in sd_set_timing()
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1008 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, in sd_set_timing()
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, in sd_set_timing()
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, in sd_set_timing()
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, in sd_set_timing()
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, in sd_set_timing()
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in sd_set_timing()
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in sd_set_timing()
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, in sd_set_timing()
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_timing()
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in sd_set_timing()
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, in sd_set_timing()