273 		clk_en_a = mci_readl(host, CLKENA);  in dw_mci_prepare_command()
355 		while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {  in dw_mci_wait_while_busy()
422 	u32 bmod = mci_readl(host, BMOD);  in dw_mci_idmac_reset()
433 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_stop_dma()
439 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_stop_dma()
584 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_start_dma()
592 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_start_dma()
708 	fifoth_val = mci_readl(host, FIFOTH);  in dw_mci_edmac_start_dma()
979 	temp = mci_readl(host, CTRL);  in dw_mci_submit_data_dma()
985 	temp = mci_readl(host, INTMASK);  in dw_mci_submit_data_dma()
1032 		temp = mci_readl(host, INTMASK);  in dw_mci_submit_data()
1037 		temp = mci_readl(host, CTRL);  in dw_mci_submit_data()
1070 		cmd_status = mci_readl(host, CMD);  in mci_send_cmd()
1292 	regs = mci_readl(slot->host, UHS_REG);  in dw_mci_set_ios()
1327 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1366 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1387 	status = mci_readl(slot->host, STATUS);  in dw_mci_card_busy()
1409 	uhs = mci_readl(host, UHS_REG);  in dw_mci_switch_voltage()
1441 			mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;  in dw_mci_get_ro()
1464 		present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))  in dw_mci_get_cd()
1495 		clk_en_a_old = mci_readl(host, CLKENA);  in dw_mci_init_card()
1524 	int_mask = mci_readl(host, INTMASK);  in dw_mci_enable_sdio_irq()
1616 			cmd->resp[3] = mci_readl(host, RESP0);  in dw_mci_command_complete()
1617 			cmd->resp[2] = mci_readl(host, RESP1);  in dw_mci_command_complete()
1618 			cmd->resp[1] = mci_readl(host, RESP2);  in dw_mci_command_complete()
1619 			cmd->resp[0] = mci_readl(host, RESP3);  in dw_mci_command_complete()
1621 			cmd->resp[0] = mci_readl(host, RESP0);  in dw_mci_command_complete()
1694 	drto_clks = mci_readl(host, TMOUT) >> 8;  in dw_mci_set_drto()
2235 			fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))  in dw_mci_read_data_pio()
2247 		status = mci_readl(host, MINTSTS);  in dw_mci_read_data_pio()
2251 		 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));  in dw_mci_read_data_pio()
2291 				 SDMMC_GET_FCNT(mci_readl(host, STATUS)))  in dw_mci_write_data_pio()
2303 		status = mci_readl(host, MINTSTS);  in dw_mci_write_data_pio()
2356 	pending = mci_readl(host, MINTSTS); /* read-only mask reg */  in dw_mci_interrupt()
2364 		    ((mci_readl(host, STATUS) >> 17) & 0x1fff))  in dw_mci_interrupt()
2463 		pending = mci_readl(host, IDSTS64);  in dw_mci_interrupt()
2471 		pending = mci_readl(host, IDSTS);  in dw_mci_interrupt()
2655 	host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));  in dw_mci_init_dma()
2671 		addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));  in dw_mci_init_dma()
2734 	ctrl = mci_readl(host, CTRL);  in dw_mci_ctrl_reset()
2740 		ctrl = mci_readl(host, CTRL);  in dw_mci_ctrl_reset()
2782 				status = mci_readl(host, STATUS);  in dw_mci_reset()
2801 		if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {  in dw_mci_reset()
2947 	temp = mci_readl(host, INTMASK);  in dw_mci_enable_cd()
3048 	i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));  in dw_mci_probe()
3095 		fifo_size = mci_readl(host, FIFOTH);  in dw_mci_probe()
3113 	host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));  in dw_mci_probe()
3130 		host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));  in dw_mci_probe()