Lines Matching refs:BIT
106 # define SEC_IPC_INPUT_STATUS_RDY BIT(0)
110 #define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0)
111 #define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1)
112 #define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5)
113 #define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17)
114 #define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18)
115 #define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19)
116 #define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21)
126 # define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */
127 # define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */
139 # define SATT2_CTRL_VALID_MSK BIT(0)
141 # define SATT2_CTRL_BRIDGE_HOST_EN_MSK BIT(12)
160 #define IPC_HHIER_SEC BIT(0)
161 #define IPC_HHIER_BRIDGE BIT(1)
170 #define IPC_HHIMR_SEC BIT(0)
171 #define IPC_HHIMR_BRIDGE BIT(1)
184 #define HICR_SEC_IPC_READINESS_HOST_RDY BIT(0)
185 #define HICR_SEC_IPC_READINESS_SEC_RDY BIT(1)
189 #define HICR_SEC_IPC_READINESS_RDY_CLR BIT(2)
197 #define HICR_HOST_ALIVENESS_RESP_ACK BIT(0)
216 #define HISR_INT_0_STS BIT(0)
217 #define HISR_INT_1_STS BIT(1)
218 #define HISR_INT_2_STS BIT(2)
219 #define HISR_INT_3_STS BIT(3)
220 #define HISR_INT_4_STS BIT(4)
221 #define HISR_INT_5_STS BIT(5)
222 #define HISR_INT_6_STS BIT(6)
223 #define HISR_INT_7_STS BIT(7)
229 #define HIER_INT_0_EN BIT(0)
230 #define HIER_INT_1_EN BIT(1)
231 #define HIER_INT_2_EN BIT(2)
232 #define HIER_INT_3_EN BIT(3)
233 #define HIER_INT_4_EN BIT(4)
234 #define HIER_INT_5_EN BIT(5)
235 #define HIER_INT_6_EN BIT(6)
236 #define HIER_INT_7_EN BIT(7)
254 #define SICR_HOST_ALIVENESS_REQ_REQUESTED BIT(0)
267 #define SICR_HOST_IPC_READINESS_HOST_RDY BIT(0)
268 #define SICR_HOST_IPC_READINESS_SEC_RDY BIT(1)
272 #define SICR_HOST_IPC_READINESS_RDY_CLR BIT(2)
282 # define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)