Lines Matching refs:dev
66 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
68 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
77 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
79 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
89 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
93 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
94 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
106 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
110 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
111 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
124 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
125 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
138 mei_hcsr_write(dev, reg); in mei_hcsr_set()
148 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
152 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
153 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
164 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
166 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
167 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
178 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
181 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_fw_status()
182 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
206 static void mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
208 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_hw_config()
209 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
213 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
214 dev->hbuf_depth = (hcsr & H_CBD) >> 24; in mei_me_hw_config()
223 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
237 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
239 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
249 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
251 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
254 mei_hcsr_write(dev, hcsr); in mei_me_intr_clear()
261 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
263 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_enable()
266 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
274 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
276 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
279 mei_hcsr_set(dev, hcsr); in mei_me_intr_disable()
287 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
289 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
293 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
304 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
306 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
309 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
318 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
320 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
331 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
333 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
345 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
347 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
348 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
349 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
351 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
352 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
353 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
357 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
358 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
368 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
370 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
374 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
376 mei_me_host_set_ready(dev); in mei_me_hw_start()
388 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
393 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
408 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
410 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
420 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
424 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
425 empty_slots = dev->hbuf_depth - filled_slots; in mei_me_hbuf_empty_slots()
428 if (filled_slots > dev->hbuf_depth) in mei_me_hbuf_empty_slots()
441 static size_t mei_me_hbuf_max_len(const struct mei_device *dev) in mei_me_hbuf_max_len() argument
443 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); in mei_me_hbuf_max_len()
456 static int mei_me_write_message(struct mei_device *dev, in mei_me_write_message() argument
468 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); in mei_me_write_message()
470 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_write_message()
471 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); in mei_me_write_message()
477 mei_me_hcbww_write(dev, *((u32 *) header)); in mei_me_write_message()
480 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_write_message()
487 mei_me_hcbww_write(dev, reg); in mei_me_write_message()
490 hcsr = mei_hcsr_read(dev) | H_IG; in mei_me_write_message()
491 mei_hcsr_set(dev, hcsr); in mei_me_write_message()
492 if (!mei_me_hw_is_ready(dev)) in mei_me_write_message()
505 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
511 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
521 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
534 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
541 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
544 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
549 hcsr = mei_hcsr_read(dev) | H_IG; in mei_me_read_slots()
550 mei_hcsr_set(dev, hcsr); in mei_me_read_slots()
559 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
561 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
565 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
569 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
578 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
580 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
584 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
590 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
601 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
603 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
607 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
609 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
613 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
614 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
615 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_enter_sync()
616 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
618 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
619 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
625 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
638 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
640 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
644 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
647 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
649 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
651 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
652 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
653 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
654 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
657 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
662 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
663 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
667 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
668 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
669 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
670 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
672 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
678 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
691 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
693 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
694 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
704 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
706 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
707 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
715 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
721 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
724 dev->version.major_version, in mei_me_pg_is_enabled()
725 dev->version.minor_version, in mei_me_pg_is_enabled()
740 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
742 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
749 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
751 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
762 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
764 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
768 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
770 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
781 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
783 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
789 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
792 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
798 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
800 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
805 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
806 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
807 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); in mei_me_d0i3_enter_sync()
808 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
810 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
816 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
818 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
820 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
825 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
826 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
827 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); in mei_me_d0i3_enter_sync()
828 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
830 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
831 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
842 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
843 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
857 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
859 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
862 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
865 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
869 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
872 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
873 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
884 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
886 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
891 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
893 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
896 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
901 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
903 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
908 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
909 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
910 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_d0i3_exit_sync()
911 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
913 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
914 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
925 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
927 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
937 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
939 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
941 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
944 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
946 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
947 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
955 static void mei_me_d0i3_intr(struct mei_device *dev) in mei_me_d0i3_intr() argument
957 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
959 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
961 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
964 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
969 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
970 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
976 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
985 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
986 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
995 static void mei_me_pg_intr(struct mei_device *dev) in mei_me_pg_intr() argument
997 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1000 mei_me_d0i3_intr(dev); in mei_me_pg_intr()
1002 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1012 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1014 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1017 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1019 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1029 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1031 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1034 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1036 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1047 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1049 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1054 mei_me_intr_enable(dev); in mei_me_hw_reset()
1056 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1062 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1069 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1071 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1072 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1080 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1081 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1087 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1090 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1093 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1096 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1098 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1116 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1117 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_irq_quick_handler()
1120 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1125 dev_dbg(dev->dev, "interrupt source 0x%08X.\n", hw->intr_source); in mei_me_irq_quick_handler()
1128 mei_hcsr_write(dev, hcsr); in mei_me_irq_quick_handler()
1145 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1150 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1152 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1156 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1157 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_me_irq_thread_handler()
1158 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1162 mei_me_pg_intr(dev); in mei_me_irq_thread_handler()
1165 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1166 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1167 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1168 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1169 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1171 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1176 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1178 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1179 rets = mei_irq_read_handler(dev, &complete_list, &slots); in mei_me_irq_thread_handler()
1187 if (rets && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1188 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", in mei_me_irq_thread_handler()
1190 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1195 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1202 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1203 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1204 rets = mei_irq_write_handler(dev, &complete_list); in mei_me_irq_thread_handler()
1205 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1208 mei_irq_compl_handler(dev, &complete_list); in mei_me_irq_thread_handler()
1211 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1212 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1336 struct mei_device *dev; in mei_me_dev_init() local
1339 dev = kzalloc(sizeof(struct mei_device) + in mei_me_dev_init()
1341 if (!dev) in mei_me_dev_init()
1343 hw = to_me_hw(dev); in mei_me_dev_init()
1345 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); in mei_me_dev_init()
1347 return dev; in mei_me_dev_init()