33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)			\  argument
35 		pci_read_config_word(dev, vsec + 0x6, dest);	\
36 		*dest >>= 4;					\
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \  argument
39 	pci_read_config_byte(dev, vsec + 0x8, dest)
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \  argument
42 	pci_read_config_byte(dev, vsec + 0x9, dest)
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \  argument
55 	pci_read_config_byte(dev, vsec + 0xa, dest)
64 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \  argument
65 	pci_read_config_word(dev, vsec + 0xc, dest)
66 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \  argument
67 	pci_read_config_byte(dev, vsec + 0xe, dest)
68 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \  argument
69 	pci_read_config_byte(dev, vsec + 0xf, dest)
70 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \  argument
71 	pci_read_config_word(dev, vsec + 0x10, dest)
73 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \  argument
74 	pci_read_config_byte(dev, vsec + 0x13, dest)
81 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \  argument
82 	pci_read_config_dword(dev, vsec + 0x20, dest)
83 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \  argument
84 	pci_read_config_dword(dev, vsec + 0x24, dest)
85 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \  argument
86 	pci_read_config_dword(dev, vsec + 0x28, dest)
87 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \  argument
88 	pci_read_config_dword(dev, vsec + 0x2c, dest)