Lines Matching refs:cxl_p1n_reg_t

55 } cxl_p1n_reg_t;  typedef
99 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
100 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
101 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
102 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
103 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
104 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
106 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
107 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
109 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
110 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
111 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
113 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
114 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
115 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
116 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
118 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
119 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
120 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
121 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
122 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
123 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
571 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)  in _cxl_p1n_addr()
577 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)  in cxl_p1n_write()
583 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)  in cxl_p1n_read()