Lines Matching refs:cxl_p1_reg_t

52 } cxl_p1_reg_t;  typedef
66 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
67 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
68 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
69 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
70 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
72 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
73 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
76 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
77 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
78 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
79 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
80 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
81 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
84 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
85 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
86 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
87 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
88 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
89 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
90 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
91 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
92 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
93 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
551 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)  in _cxl_p1_addr()
557 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)  in cxl_p1_write()
563 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)  in cxl_p1_read()