155 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);  in __rtsx_pci_write_phy_register()
156 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));  in __rtsx_pci_write_phy_register()
157 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);  in __rtsx_pci_write_phy_register()
158 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);  in __rtsx_pci_write_phy_register()
198 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);  in __rtsx_pci_read_phy_register()
199 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);  in __rtsx_pci_read_phy_register()
221 	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);  in __rtsx_pci_read_phy_register()
222 	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);  in __rtsx_pci_read_phy_register()
256 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,  in rtsx_pci_add_cmd()  function
277 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
492 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
506 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
535 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
549 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
568 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_set_pull_ctl()
708 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in rtsx_pci_switch_clock()
710 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,  in rtsx_pci_switch_clock()
712 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rtsx_pci_switch_clock()
713 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,  in rtsx_pci_switch_clock()
715 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rtsx_pci_switch_clock()
716 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);  in rtsx_pci_switch_clock()
718 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
720 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
1014 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);  in rtsx_pci_init_hw()
1016 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);  in rtsx_pci_init_hw()
1018 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);  in rtsx_pci_init_hw()
1020 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);  in rtsx_pci_init_hw()
1022 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,  in rtsx_pci_init_hw()
1025 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,  in rtsx_pci_init_hw()
1027 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);  in rtsx_pci_init_hw()
1029 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);  in rtsx_pci_init_hw()
1031 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in rtsx_pci_init_hw()
1036 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);  in rtsx_pci_init_hw()
1041 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);  in rtsx_pci_init_hw()
1047 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);  in rtsx_pci_init_hw()