28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)  in rts5249_get_ic_version()  argument
32 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);  in rts5249_get_ic_version()
36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)  in rts5249_fill_driving()  argument
54 		drive_sel = pcr->sd30_drive_sel_3v3;  in rts5249_fill_driving()
57 		drive_sel = pcr->sd30_drive_sel_1v8;  in rts5249_fill_driving()
60 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,  in rts5249_fill_driving()
62 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,  in rts5249_fill_driving()
64 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,  in rts5249_fill_driving()
68 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)  in rtsx_base_fetch_vendor_settings()  argument
72 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);  in rtsx_base_fetch_vendor_settings()
73 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);  in rtsx_base_fetch_vendor_settings()
76 		pcr_dbg(pcr, "skip fetch vendor setting\n");  in rtsx_base_fetch_vendor_settings()
80 	pcr->aspm_en = rtsx_reg_to_aspm(reg);  in rtsx_base_fetch_vendor_settings()
81 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);  in rtsx_base_fetch_vendor_settings()
82 	pcr->card_drive_sel &= 0x3F;  in rtsx_base_fetch_vendor_settings()
83 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);  in rtsx_base_fetch_vendor_settings()
85 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);  in rtsx_base_fetch_vendor_settings()
86 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);  in rtsx_base_fetch_vendor_settings()
87 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);  in rtsx_base_fetch_vendor_settings()
89 		pcr->flags |= PCR_REVERSE_SOCKET;  in rtsx_base_fetch_vendor_settings()
92 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)  in rtsx_base_force_power_down()  argument
95 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);  in rtsx_base_force_power_down()
96 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);  in rtsx_base_force_power_down()
97 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);  in rtsx_base_force_power_down()
100 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,  in rtsx_base_force_power_down()
103 	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);  in rtsx_base_force_power_down()
106 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)  in rts5249_extra_init_hw()  argument
108 	rtsx_pci_init_cmd(pcr);  in rts5249_extra_init_hw()
111 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);  in rts5249_extra_init_hw()
113 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);  in rts5249_extra_init_hw()
115 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);  in rts5249_extra_init_hw()
117 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);  in rts5249_extra_init_hw()
118 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);  in rts5249_extra_init_hw()
120 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);  in rts5249_extra_init_hw()
122 	rts5249_fill_driving(pcr, OUTPUT_3V3);  in rts5249_extra_init_hw()
123 	if (pcr->flags & PCR_REVERSE_SOCKET)  in rts5249_extra_init_hw()
124 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);  in rts5249_extra_init_hw()
126 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);  in rts5249_extra_init_hw()
128 	return rtsx_pci_send_cmd(pcr, 100);  in rts5249_extra_init_hw()
131 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)  in rts5249_optimize_phy()  argument
135 	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);  in rts5249_optimize_phy()
139 	err = rtsx_pci_write_phy_register(pcr, PHY_REV,  in rts5249_optimize_phy()
150 	err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,  in rts5249_optimize_phy()
156 	err = rtsx_pci_write_phy_register(pcr, PHY_PCR,  in rts5249_optimize_phy()
163 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,  in rts5249_optimize_phy()
170 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,  in rts5249_optimize_phy()
177 	err = rtsx_pci_write_phy_register(pcr, PHY_RDR,  in rts5249_optimize_phy()
181 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,  in rts5249_optimize_phy()
185 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,  in rts5249_optimize_phy()
191 	return rtsx_pci_write_phy_register(pcr, PHY_TUNE,  in rts5249_optimize_phy()
197 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)  in rtsx_base_turn_on_led()  argument
199 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);  in rtsx_base_turn_on_led()
202 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)  in rtsx_base_turn_off_led()  argument
204 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);  in rtsx_base_turn_off_led()
207 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)  in rtsx_base_enable_auto_blink()  argument
209 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);  in rtsx_base_enable_auto_blink()
212 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)  in rtsx_base_disable_auto_blink()  argument
214 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);  in rtsx_base_disable_auto_blink()
217 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)  in rtsx_base_card_power_on()  argument
221 	rtsx_pci_init_cmd(pcr);  in rtsx_base_card_power_on()
222 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rtsx_base_card_power_on()
224 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rtsx_base_card_power_on()
226 	err = rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_card_power_on()
232 	rtsx_pci_init_cmd(pcr);  in rtsx_base_card_power_on()
233 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rtsx_base_card_power_on()
235 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rtsx_base_card_power_on()
237 	return rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_card_power_on()
240 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)  in rtsx_base_card_power_off()  argument
242 	rtsx_pci_init_cmd(pcr);  in rtsx_base_card_power_off()
243 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,  in rtsx_base_card_power_off()
245 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,  in rtsx_base_card_power_off()
247 	return rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_card_power_off()
250 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)  in rtsx_base_switch_output_voltage()  argument
257 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,  in rtsx_base_switch_output_voltage()
264 		if (CHK_PCI_PID(pcr, 0x5249)) {  in rtsx_base_switch_output_voltage()
265 			err = rtsx_pci_update_phy(pcr, PHY_BACR,  in rtsx_base_switch_output_voltage()
272 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,  in rtsx_base_switch_output_voltage()
278 		pcr_dbg(pcr, "unknown output voltage %d\n", voltage);  in rtsx_base_switch_output_voltage()
283 	rtsx_pci_init_cmd(pcr);  in rtsx_base_switch_output_voltage()
284 	rts5249_fill_driving(pcr, voltage);  in rtsx_base_switch_output_voltage()
285 	return rtsx_pci_send_cmd(pcr, 100);  in rtsx_base_switch_output_voltage()
354 void rts5249_init_params(struct rtsx_pcr *pcr)  in rts5249_init_params()  argument
356 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;  in rts5249_init_params()
357 	pcr->num_slots = 2;  in rts5249_init_params()
358 	pcr->ops = &rts5249_pcr_ops;  in rts5249_init_params()
360 	pcr->flags = 0;  in rts5249_init_params()
361 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;  in rts5249_init_params()
362 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;  in rts5249_init_params()
363 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;  in rts5249_init_params()
364 	pcr->aspm_en = ASPM_L1_EN;  in rts5249_init_params()
365 	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);  in rts5249_init_params()
366 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);  in rts5249_init_params()
368 	pcr->ic_version = rts5249_get_ic_version(pcr);  in rts5249_init_params()
369 	pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;  in rts5249_init_params()
370 	pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;  in rts5249_init_params()
371 	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;  in rts5249_init_params()
372 	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;  in rts5249_init_params()
374 	pcr->reg_pm_ctrl3 = PM_CTRL3;  in rts5249_init_params()
377 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)  in rts524a_write_phy()  argument
381 	return __rtsx_pci_write_phy_register(pcr, addr, val);  in rts524a_write_phy()
384 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)  in rts524a_read_phy()  argument
388 	return __rtsx_pci_read_phy_register(pcr, addr, val);  in rts524a_read_phy()
391 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)  in rts524a_optimize_phy()  argument
395 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,  in rts524a_optimize_phy()
400 	rtsx_pci_write_phy_register(pcr, PHY_PCR,  in rts524a_optimize_phy()
403 	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,  in rts524a_optimize_phy()
406 	if (is_version(pcr, 0x524A, IC_VER_A)) {  in rts524a_optimize_phy()
407 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,  in rts524a_optimize_phy()
409 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,  in rts524a_optimize_phy()
412 		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,  in rts524a_optimize_phy()
415 		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,  in rts524a_optimize_phy()
417 		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,  in rts524a_optimize_phy()
427 	rtsx_pci_write_phy_register(pcr, PHY_ANA08,  in rts524a_optimize_phy()
434 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)  in rts524a_extra_init_hw()  argument
436 	rts5249_extra_init_hw(pcr);  in rts524a_extra_init_hw()
438 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,  in rts524a_extra_init_hw()
440 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);  in rts524a_extra_init_hw()
441 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,  in rts524a_extra_init_hw()
443 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);  in rts524a_extra_init_hw()
444 	if (is_version(pcr, 0x524A, IC_VER_A)) {  in rts524a_extra_init_hw()
445 		rtsx_pci_write_register(pcr, LDO_DV18_CFG,  in rts524a_extra_init_hw()
447 		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,  in rts524a_extra_init_hw()
449 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts524a_extra_init_hw()
451 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts524a_extra_init_hw()
453 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,  in rts524a_extra_init_hw()
455 		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,  in rts524a_extra_init_hw()
478 void rts524a_init_params(struct rtsx_pcr *pcr)  in rts524a_init_params()  argument
480 	rts5249_init_params(pcr);  in rts524a_init_params()
482 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;  in rts524a_init_params()
483 	pcr->ops = &rts524a_pcr_ops;  in rts524a_init_params()
486 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)  in rts525a_card_power_on()  argument
488 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1,  in rts525a_card_power_on()
490 	return rtsx_base_card_power_on(pcr, card);  in rts525a_card_power_on()
493 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)  in rts525a_switch_output_voltage()  argument
497 		rtsx_pci_write_register(pcr, LDO_CONFIG2,  in rts525a_switch_output_voltage()
499 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);  in rts525a_switch_output_voltage()
502 		rtsx_pci_write_register(pcr, LDO_CONFIG2,  in rts525a_switch_output_voltage()
504 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,  in rts525a_switch_output_voltage()
511 	rtsx_pci_init_cmd(pcr);  in rts525a_switch_output_voltage()
512 	rts5249_fill_driving(pcr, voltage);  in rts525a_switch_output_voltage()
513 	return rtsx_pci_send_cmd(pcr, 100);  in rts525a_switch_output_voltage()
516 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)  in rts525a_optimize_phy()  argument
520 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,  in rts525a_optimize_phy()
525 	rtsx_pci_write_phy_register(pcr, _PHY_FLD0,  in rts525a_optimize_phy()
530 	rtsx_pci_write_phy_register(pcr, _PHY_ANA03,  in rts525a_optimize_phy()
534 	if (is_version(pcr, 0x525A, IC_VER_A))  in rts525a_optimize_phy()
535 		rtsx_pci_write_phy_register(pcr, _PHY_REV0,  in rts525a_optimize_phy()
542 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)  in rts525a_extra_init_hw()  argument
544 	rts5249_extra_init_hw(pcr);  in rts525a_extra_init_hw()
546 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);  in rts525a_extra_init_hw()
547 	if (is_version(pcr, 0x525A, IC_VER_A)) {  in rts525a_extra_init_hw()
548 		rtsx_pci_write_register(pcr, L1SUB_CONFIG2,  in rts525a_extra_init_hw()
550 		rtsx_pci_write_register(pcr, RREF_CFG,  in rts525a_extra_init_hw()
552 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,  in rts525a_extra_init_hw()
554 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,  in rts525a_extra_init_hw()
556 		rtsx_pci_write_register(pcr, LDO_AV12S_CFG,  in rts525a_extra_init_hw()
558 		rtsx_pci_write_register(pcr, LDO_VCC_CFG0,  in rts525a_extra_init_hw()
560 		rtsx_pci_write_register(pcr, OOBS_CONFIG,  in rts525a_extra_init_hw()
581 void rts525a_init_params(struct rtsx_pcr *pcr)  in rts525a_init_params()  argument
583 	rts5249_init_params(pcr);  in rts525a_init_params()
585 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;  in rts525a_init_params()
586 	pcr->ops = &rts525a_pcr_ops;  in rts525a_init_params()