Lines Matching refs:prcmu_base
52 #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118)
56 #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8)
59 #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114)
63 #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98)
67 #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0)
68 #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C)
69 #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4)
70 #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0)
71 #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c)
72 #define PRCM_SRAM_A9 (prcmu_base + 0x308)
78 #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc)
79 #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100)
80 #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104)
82 #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334)
87 #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C)
88 #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494)
89 #define PRCM_HOLD_EVT (prcmu_base + 0x174)
91 #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0)
96 #define PRCM_ITSTATUS0 (prcmu_base + 0x148)
97 #define PRCM_ITSTATUS1 (prcmu_base + 0x150)
98 #define PRCM_ITSTATUS2 (prcmu_base + 0x158)
99 #define PRCM_ITSTATUS3 (prcmu_base + 0x160)
100 #define PRCM_ITSTATUS4 (prcmu_base + 0x168)
101 #define PRCM_ITSTATUS5 (prcmu_base + 0x484)
102 #define PRCM_ITCLEAR5 (prcmu_base + 0x488)
103 #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018)
106 #define PRCM_APE_SOFTRST (prcmu_base + 0x228)
109 #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420)
110 #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424)
116 #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080)
117 #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084)
118 #define PRCM_PLLARM_FREQ (prcmu_base + 0x088)
119 #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C)
129 #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500)
130 #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504)
131 #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
132 #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530)
133 #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C)
134 #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
135 #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4)
136 #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8)
165 #define PRCM_CLKOCR (prcmu_base + 0x1CC)
172 #define PRCM_EPOD_C_SET (prcmu_base + 0x410)
173 #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304)
176 #define PRCM_POWER_STATE_SET (prcmu_base + 0x254)
179 #define PRCM_DSI_SW_RESET (prcmu_base + 0x324)
180 #define PRCM_GPIOCR (prcmu_base + 0x138)
185 #define PRCM_SEM (prcmu_base + 0x400)
188 #define PRCM_TCR (prcmu_base + 0x1C8)
216 #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438)
217 #define PRCM_CGATING_BYPASS (prcmu_base + 0x134)
221 #define PRCM_RESOUTN_SET (prcmu_base + 0x214)
222 #define PRCM_RESOUTN_CLR (prcmu_base + 0x218)
225 #define PRCM_APE_SOFTRST (prcmu_base + 0x228)