599 		if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)  in db8500_prcmu_enable_dsipll()
625 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)  in db8500_prcmu_set_display_clocks()
642 	return readl(prcmu_base + reg);  in db8500_prcmu_read()
660 	val = readl(prcmu_base + reg);  in db8500_prcmu_write_masked()
761 	val = readl(PRCM_CLKOCR);  in prcmu_config_clkout()
792 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in db8500_prcmu_set_power_state()
835 		while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in config_wakeups()
905 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_arm_opp()
976 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)  in request_even_slower_clocks()
983 		val = readl(prcmu_base + clock_reg[i]);  in request_even_slower_clocks()
1031 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_set_ape_opp()
1096 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_request_ape_opp_100_voltage()
1125 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in prcmu_release_usb_wakeup_state()
1156 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in request_pll()
1208 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))  in db8500_prcmu_set_epod()
1305 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))  in request_sysclk()
1350 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)  in request_clock()
1353 	val = readl(prcmu_base + clk_mgt[clock].offset);  in request_clock()
1376 		val = readl(PRCM_CGATING_BYPASS);  in request_sga_clock()
1383 		val = readl(PRCM_CGATING_BYPASS);  in request_sga_clock()
1392 	return (readl(PRCM_PLLDSI_LOCKP) &  in plldsi_locked()
1408 	val = readl(PRCM_PLLDSI_ENABLE);  in request_plldsi()
1444 	val = readl(PRCM_DSI_PLLOUT_SEL);  in request_dsiclk()
1456 	val = readl(PRCM_DSITVCLK_DIV);  in request_dsiescclk()
1500 	val = readl(reg);  in pll_rate()
1536 	val = readl(prcmu_base + clk_mgt[clock].offset);  in clock_rate()
1575 	r = readl(PRCM_ARM_CHGCLKREQ);  in armss_rate()
1587 		r = readl(PRCM_ARMCLKFIX_MGT);  in armss_rate()
1603 	divsel = readl(PRCM_DSI_PLLOUT_SEL);  in dsiclk_rate()
1628 	div = readl(PRCM_DSITVCLK_DIV);  in dsiescclk_rate()
1694 	val = readl(prcmu_base + clk_mgt[clock].offset);  in round_clock_rate()
1838 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)  in set_clock_rate()
1841 	val = readl(prcmu_base + clk_mgt[clock].offset);  in set_clock_rate()
1954 	val = readl(PRCM_DSI_PLLOUT_SEL);  in set_dsiclk_rate()
1966 	val = readl(PRCM_DSITVCLK_DIV);  in set_dsiescclk_rate()
1995 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_esram0_deep_sleep()
2017 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotdog()
2035 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in db8500_prcmu_config_hotmon()
2056 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in config_hot_period()
2088 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))  in prcmu_a9wdog()
2171 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_read()
2221 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))  in prcmu_abb_write_masked()
2273 	val = readl(PRCM_HOSTACCESS_REQ);  in prcmu_ac_wake_req()
2313 	val = readl(PRCM_HOSTACCESS_REQ);  in prcmu_ac_sleep_req()
2367 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))  in db8500_prcmu_modem_reset()
2388 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))  in ack_dbb_wakeup()
2415 			ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);  in read_mailbox_0()
2417 			ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);  in read_mailbox_0()
2538 	bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);  in prcmu_irq_handler()
2706 	version = readl(tcpm_base + version_offset);  in dbx500_fw_version_init()
2762 	val = readl(PRCM_A9PL_FORCE_CLKEN);  in init_prcm_registers()