Lines Matching refs:div

725 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)  in prcmu_config_clkout()  argument
736 BUG_ON(div > 63); in prcmu_config_clkout()
739 if (!div && !requests[clkout]) in prcmu_config_clkout()
747 (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); in prcmu_config_clkout()
754 (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); in prcmu_config_clkout()
763 if (div) { in prcmu_config_clkout()
776 requests[clkout] += (div ? 1 : -1); in prcmu_config_clkout()
981 u32 div; in request_even_slower_clocks() local
984 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); in request_even_slower_clocks()
986 if ((div <= 1) || (div > 15)) { in request_even_slower_clocks()
988 div, __func__); in request_even_slower_clocks()
991 div <<= 1; in request_even_slower_clocks()
993 if (div <= 2) in request_even_slower_clocks()
995 div >>= 1; in request_even_slower_clocks()
998 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); in request_even_slower_clocks()
1498 u32 div = 1; in pll_rate() local
1507 div *= d; in pll_rate()
1511 div *= d; in pll_rate()
1514 div *= 2; in pll_rate()
1521 div *= 2; in pll_rate()
1523 (void)do_div(rate, div); in pll_rate()
1601 u32 div = 1; in dsiclk_rate() local
1613 div *= 2; in dsiclk_rate()
1615 div *= 2; in dsiclk_rate()
1618 PLL_RAW) / div; in dsiclk_rate()
1626 u32 div; in dsiescclk_rate() local
1628 div = readl(PRCM_DSITVCLK_DIV); in dsiescclk_rate()
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1630 return clock_rate(PRCMU_TVCLK) / max((u32)1, div); in dsiescclk_rate()
1677 u32 div; in clock_divider() local
1679 div = (src_rate / rate); in clock_divider()
1680 if (div == 0) in clock_divider()
1682 if (rate < (src_rate / div)) in clock_divider()
1683 div++; in clock_divider()
1684 return div; in clock_divider()
1690 u32 div; in round_clock_rate() local
1697 div = clock_divider(src_rate, rate); in round_clock_rate()
1700 if (div > 2) in round_clock_rate()
1701 div = 2; in round_clock_rate()
1703 div = 1; in round_clock_rate()
1705 } else if ((clock == PRCMU_SGACLK) && (div == 3)) { in round_clock_rate()
1712 rounded_rate = (src_rate / min(div, (u32)31)); in round_clock_rate()
1787 u32 div; in round_dsiclk_rate() local
1793 div = clock_divider(src_rate, rate); in round_dsiclk_rate()
1794 rounded_rate = (src_rate / ((div > 2) ? 4 : div)); in round_dsiclk_rate()
1801 u32 div; in round_dsiescclk_rate() local
1806 div = clock_divider(src_rate, rate); in round_dsiescclk_rate()
1807 rounded_rate = (src_rate / min(div, (u32)255)); in round_dsiescclk_rate()
1831 u32 div; in set_clock_rate() local
1844 div = clock_divider(src_rate, rate); in set_clock_rate()
1847 if (div > 1) in set_clock_rate()
1855 if (div == 3) { in set_clock_rate()
1861 div = 0; in set_clock_rate()
1864 val |= min(div, (u32)31); in set_clock_rate()
1867 val |= min(div, (u32)31); in set_clock_rate()
1945 u32 div; in set_dsiclk_rate() local
1947 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, in set_dsiclk_rate()
1950 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : in set_dsiclk_rate()
1951 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : in set_dsiclk_rate()
1963 u32 div; in set_dsiescclk_rate() local
1965 div = clock_divider(clock_rate(PRCMU_TVCLK), rate); in set_dsiescclk_rate()
1968 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()