152 		int bank;  in asic3_irq_demux()  local
164 		for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {  in asic3_irq_demux()
165 			if (status & (1 << bank)) {  in asic3_irq_demux()
169 				       + bank * ASIC3_GPIO_BASE_INCR;  in asic3_irq_demux()
189 						(ASIC3_GPIOS_PER_BANK * bank)  in asic3_irq_demux()
192 					if (asic->irq_bothedge[bank] & bit)  in asic3_irq_demux()
228 	u32 val, bank, index;  in asic3_mask_gpio_irq()  local
231 	bank = asic3_irq_to_bank(asic, data->irq);  in asic3_mask_gpio_irq()
235 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_mask_gpio_irq()
237 	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);  in asic3_mask_gpio_irq()
265 	u32 val, bank, index;  in asic3_unmask_gpio_irq()  local
268 	bank = asic3_irq_to_bank(asic, data->irq);  in asic3_unmask_gpio_irq()
272 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_unmask_gpio_irq()
274 	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);  in asic3_unmask_gpio_irq()
302 	u32 bank, index;  in asic3_gpio_irq_type()  local
306 	bank = asic3_irq_to_bank(asic, data->irq);  in asic3_gpio_irq_type()
312 				    bank + ASIC3_GPIO_LEVEL_TRIGGER);  in asic3_gpio_irq_type()
314 				   bank + ASIC3_GPIO_EDGE_TRIGGER);  in asic3_gpio_irq_type()
316 				      bank + ASIC3_GPIO_TRIGGER_TYPE);  in asic3_gpio_irq_type()
346 	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,  in asic3_gpio_irq_type()
348 	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,  in asic3_gpio_irq_type()
350 	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,  in asic3_gpio_irq_type()
359 	u32 bank, index;  in asic3_gpio_irq_set_wake()  local
362 	bank = asic3_irq_to_bank(asic, data->irq);  in asic3_gpio_irq_set_wake()
366 	asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);  in asic3_gpio_irq_set_wake()