Lines Matching refs:asic
92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) in asic3_write_register() argument
94 iowrite16(value, asic->mapping + in asic3_write_register()
95 (reg >> asic->bus_shift)); in asic3_write_register()
99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg) in asic3_read_register() argument
101 return ioread16(asic->mapping + in asic3_read_register()
102 (reg >> asic->bus_shift)); in asic3_read_register()
106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) in asic3_set_register() argument
111 spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
112 val = asic3_read_register(asic, reg); in asic3_set_register()
117 asic3_write_register(asic, reg, val); in asic3_set_register()
118 spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
126 static void asic3_irq_flip_edge(struct asic3 *asic, in asic3_irq_flip_edge() argument
132 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_flip_edge()
133 edge = asic3_read_register(asic, in asic3_irq_flip_edge()
136 asic3_write_register(asic, in asic3_irq_flip_edge()
138 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_flip_edge()
143 struct asic3 *asic = irq_desc_get_handler_data(desc); in asic3_irq_demux() local
154 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
155 status = asic3_read_register(asic, in asic3_irq_demux()
157 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
171 spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
172 istat = asic3_read_register(asic, in asic3_irq_demux()
176 asic3_write_register(asic, in asic3_irq_demux()
179 spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
188 irqnr = asic->irq_base + in asic3_irq_demux()
192 if (asic->irq_bothedge[bank] & bit) in asic3_irq_demux()
193 asic3_irq_flip_edge(asic, base, in asic3_irq_demux()
203 generic_handle_irq(asic->irq_base + i); in asic3_irq_demux()
208 dev_err(asic->dev, "interrupt processing overrun\n"); in asic3_irq_demux()
211 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) in asic3_irq_to_bank() argument
215 n = (irq - asic->irq_base) >> 4; in asic3_irq_to_bank()
220 static inline int asic3_irq_to_index(struct asic3 *asic, int irq) in asic3_irq_to_index() argument
222 return (irq - asic->irq_base) & 0xf; in asic3_irq_to_index()
227 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_gpio_irq() local
231 bank = asic3_irq_to_bank(asic, data->irq); in asic3_mask_gpio_irq()
232 index = asic3_irq_to_index(asic, data->irq); in asic3_mask_gpio_irq()
234 spin_lock_irqsave(&asic->lock, flags); in asic3_mask_gpio_irq()
235 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_mask_gpio_irq()
237 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_mask_gpio_irq()
238 spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_gpio_irq()
243 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_irq() local
247 spin_lock_irqsave(&asic->lock, flags); in asic3_mask_irq()
248 regval = asic3_read_register(asic, in asic3_mask_irq()
253 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_mask_irq()
255 asic3_write_register(asic, in asic3_mask_irq()
259 spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_irq()
264 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_gpio_irq() local
268 bank = asic3_irq_to_bank(asic, data->irq); in asic3_unmask_gpio_irq()
269 index = asic3_irq_to_index(asic, data->irq); in asic3_unmask_gpio_irq()
271 spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_gpio_irq()
272 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_unmask_gpio_irq()
274 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_unmask_gpio_irq()
275 spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_gpio_irq()
280 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_irq() local
284 spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_irq()
285 regval = asic3_read_register(asic, in asic3_unmask_irq()
290 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_unmask_irq()
292 asic3_write_register(asic, in asic3_unmask_irq()
296 spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_irq()
301 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_type() local
306 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_type()
307 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_type()
310 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_irq_type()
311 level = asic3_read_register(asic, in asic3_gpio_irq_type()
313 edge = asic3_read_register(asic, in asic3_gpio_irq_type()
315 trigger = asic3_read_register(asic, in asic3_gpio_irq_type()
317 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; in asic3_gpio_irq_type()
327 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) in asic3_gpio_irq_type()
331 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; in asic3_gpio_irq_type()
344 dev_notice(asic->dev, "irq type not changed\n"); in asic3_gpio_irq_type()
346 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, in asic3_gpio_irq_type()
348 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, in asic3_gpio_irq_type()
350 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, in asic3_gpio_irq_type()
352 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_irq_type()
358 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_set_wake() local
362 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_set_wake()
363 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_set_wake()
366 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on); in asic3_gpio_irq_set_wake()
389 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_probe() local
397 asic->irq_nr = ret; in asic3_irq_probe()
401 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_irq_probe()
404 irq_base = asic->irq_base; in asic3_irq_probe()
407 if (irq < asic->irq_base + ASIC3_NUM_GPIOS) in asic3_irq_probe()
412 irq_set_chip_data(irq, asic); in asic3_irq_probe()
417 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), in asic3_irq_probe()
420 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic); in asic3_irq_probe()
421 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); in asic3_irq_probe()
428 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_remove() local
431 irq_base = asic->irq_base; in asic3_irq_remove()
438 irq_set_chained_handler(asic->irq_nr, NULL); in asic3_irq_remove()
448 struct asic3 *asic; in asic3_gpio_direction() local
450 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_direction()
454 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_direction()
459 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_direction()
461 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); in asic3_gpio_direction()
469 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); in asic3_gpio_direction()
471 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_direction()
494 struct asic3 *asic; in asic3_gpio_get() local
496 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_get()
500 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_get()
505 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; in asic3_gpio_get()
514 struct asic3 *asic; in asic3_gpio_set() local
516 asic = container_of(chip, struct asic3, gpio); in asic3_gpio_set()
520 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_set()
527 spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_set()
529 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); in asic3_gpio_set()
536 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); in asic3_gpio_set()
538 spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_set()
545 struct asic3 *asic = container_of(chip, struct asic3, gpio); in asic3_gpio_to_irq() local
547 return asic->irq_base + offset; in asic3_gpio_to_irq()
553 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_probe() local
564 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); in asic3_gpio_probe()
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); in asic3_gpio_probe()
566 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); in asic3_gpio_probe()
567 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); in asic3_gpio_probe()
587 asic3_write_register(asic, in asic3_gpio_probe()
591 asic3_write_register(asic, in asic3_gpio_probe()
594 asic3_write_register(asic, in asic3_gpio_probe()
600 return gpiochip_add(&asic->gpio); in asic3_gpio_probe()
605 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_remove() local
607 gpiochip_remove(&asic->gpio); in asic3_gpio_remove()
611 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_enable() argument
616 spin_lock_irqsave(&asic->lock, flags); in asic3_clk_enable()
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_enable()
620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_enable()
622 spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_enable()
625 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_disable() argument
632 spin_lock_irqsave(&asic->lock, flags); in asic3_clk_disable()
634 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_disable()
636 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_disable()
638 spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_disable()
662 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_enable() local
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_enable()
666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_enable()
667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_enable()
671 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
674 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
677 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_enable()
686 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_disable() local
688 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_disable()
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_disable()
692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_disable()
693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_disable()
710 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_pwr() local
712 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_pwr()
717 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_clk_div() local
719 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_clk_div()
743 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_enable() local
746 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
748 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
750 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
752 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
755 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_enable()
759 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_enable()
763 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_mmc_enable()
766 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_enable()
767 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_enable()
770 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mmc_enable()
774 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
778 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, in asic3_mmc_enable()
786 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_disable() local
789 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_disable()
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_disable()
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_disable()
795 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_disable()
796 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_disable()
821 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_enable() local
823 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_enable()
831 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_disable() local
833 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_disable()
841 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_suspend() local
843 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) in asic3_leds_suspend()
846 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_suspend()
882 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_probe() local
888 dev_dbg(asic->dev, "no SDIO MEM resource\n"); in asic3_mfd_probe()
892 dev_dbg(asic->dev, "no SDIO IRQ resource\n"); in asic3_mfd_probe()
895 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mfd_probe()
898 ds1wm_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
899 ds1wm_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
903 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) + in asic3_mfd_probe()
905 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); in asic3_mfd_probe()
906 if (!asic->tmio_cnf) { in asic3_mfd_probe()
908 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); in asic3_mfd_probe()
912 asic3_mmc_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
913 asic3_mmc_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
918 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL); in asic3_mfd_probe()
948 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_remove() local
951 iounmap(asic->tmio_cnf); in asic3_mfd_remove()
958 struct asic3 *asic; in asic3_probe() local
963 asic = devm_kzalloc(&pdev->dev, in asic3_probe()
965 if (asic == NULL) { in asic3_probe()
970 spin_lock_init(&asic->lock); in asic3_probe()
971 platform_set_drvdata(pdev, asic); in asic3_probe()
972 asic->dev = &pdev->dev; in asic3_probe()
976 dev_err(asic->dev, "no MEM resource\n"); in asic3_probe()
980 asic->mapping = ioremap(mem->start, resource_size(mem)); in asic3_probe()
981 if (!asic->mapping) { in asic3_probe()
982 dev_err(asic->dev, "Couldn't ioremap\n"); in asic3_probe()
986 asic->irq_base = pdata->irq_base; in asic3_probe()
989 asic->bus_shift = 2 - (resource_size(mem) >> 12); in asic3_probe()
992 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
996 dev_err(asic->dev, "Couldn't probe IRQs\n"); in asic3_probe()
1000 asic->gpio.label = "asic3"; in asic3_probe()
1001 asic->gpio.base = pdata->gpio_base; in asic3_probe()
1002 asic->gpio.ngpio = ASIC3_NUM_GPIOS; in asic3_probe()
1003 asic->gpio.get = asic3_gpio_get; in asic3_probe()
1004 asic->gpio.set = asic3_gpio_set; in asic3_probe()
1005 asic->gpio.direction_input = asic3_gpio_direction_input; in asic3_probe()
1006 asic->gpio.direction_output = asic3_gpio_direction_output; in asic3_probe()
1007 asic->gpio.to_irq = asic3_gpio_to_irq; in asic3_probe()
1013 dev_err(asic->dev, "GPIO probe failed\n"); in asic3_probe()
1020 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); in asic3_probe()
1024 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_probe()
1027 dev_info(asic->dev, "ASIC3 Core driver\n"); in asic3_probe()
1035 iounmap(asic->mapping); in asic3_probe()
1043 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_remove() local
1045 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_remove()
1055 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); in asic3_remove()
1057 iounmap(asic->mapping); in asic3_remove()