80 	u32 value;  in tegra_mc_setup_latency_allowance()  local
86 	value = readl(mc->regs + MC_EMEM_ARB_CFG);  in tegra_mc_setup_latency_allowance()
87 	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;  in tegra_mc_setup_latency_allowance()
88 	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);  in tegra_mc_setup_latency_allowance()
89 	writel(value, mc->regs + MC_EMEM_ARB_CFG);  in tegra_mc_setup_latency_allowance()
94 		u32 value;  in tegra_mc_setup_latency_allowance()  local
96 		value = readl(mc->regs + la->reg);  in tegra_mc_setup_latency_allowance()
97 		value &= ~(la->mask << la->shift);  in tegra_mc_setup_latency_allowance()
98 		value |= (la->def & la->mask) << la->shift;  in tegra_mc_setup_latency_allowance()
99 		writel(value, mc->regs + la->reg);  in tegra_mc_setup_latency_allowance()
266 		u32 value;  in tegra_mc_irq()  local
268 		value = mc_readl(mc, MC_ERR_STATUS);  in tegra_mc_irq()
272 			addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &  in tegra_mc_irq()
278 		if (value & MC_ERR_STATUS_RW)  in tegra_mc_irq()
283 		if (value & MC_ERR_STATUS_SECURITY)  in tegra_mc_irq()
288 		id = value & mc->soc->client_id_mask;  in tegra_mc_irq()
297 		type = (value & MC_ERR_STATUS_TYPE_MASK) >>  in tegra_mc_irq()
301 		switch (value & MC_ERR_STATUS_TYPE_MASK) {  in tegra_mc_irq()
306 			if (value & MC_ERR_STATUS_READABLE)  in tegra_mc_irq()
311 			if (value & MC_ERR_STATUS_WRITABLE)  in tegra_mc_irq()
316 			if (value & MC_ERR_STATUS_NONSECURE)  in tegra_mc_irq()
330 		value = mc_readl(mc, MC_ERR_ADR);  in tegra_mc_irq()
331 		addr |= value;  in tegra_mc_irq()
349 	u32 value;  in tegra_mc_probe()  local
417 	value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |  in tegra_mc_probe()
421 	mc_writel(mc, value, MC_INTMASK);  in tegra_mc_probe()