Lines Matching refs:tim1
437 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw() local
440 tim1 |= val << T_WTR_SHIFT; in get_sdram_tim_1_shdw()
446 tim1 |= (val - 1) << T_RRD_SHIFT; in get_sdram_tim_1_shdw()
449 tim1 |= val << T_RC_SHIFT; in get_sdram_tim_1_shdw()
452 tim1 |= (val - 1) << T_RAS_SHIFT; in get_sdram_tim_1_shdw()
455 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw()
458 tim1 |= val << T_RCD_SHIFT; in get_sdram_tim_1_shdw()
461 tim1 |= val << T_RP_SHIFT; in get_sdram_tim_1_shdw()
463 return tim1; in get_sdram_tim_1_shdw()
470 u32 tim1 = 0, val = 0; in get_sdram_tim_1_shdw_derated() local
473 tim1 = val << T_WTR_SHIFT; in get_sdram_tim_1_shdw_derated()
485 tim1 |= val << T_RRD_SHIFT; in get_sdram_tim_1_shdw_derated()
488 tim1 |= (val - 1) << T_RC_SHIFT; in get_sdram_tim_1_shdw_derated()
492 tim1 |= val << T_RAS_SHIFT; in get_sdram_tim_1_shdw_derated()
495 tim1 |= val << T_WR_SHIFT; in get_sdram_tim_1_shdw_derated()
498 tim1 |= (val - 1) << T_RCD_SHIFT; in get_sdram_tim_1_shdw_derated()
501 tim1 |= (val - 1) << T_RP_SHIFT; in get_sdram_tim_1_shdw_derated()
503 return tim1; in get_sdram_tim_1_shdw_derated()
924 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local
930 tim1 = regs->sdram_tim1_shdw; in setup_temperature_sensitive_regs()
942 tim1 = regs->sdram_tim1_shdw_derated; in setup_temperature_sensitive_regs()
948 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); in setup_temperature_sensitive_regs()